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ORCIDHans-Joachim Wunderlich
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- affiliation: University of Stuttgart, Germany
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2020 – today
- 2024
[j59]Somayeh Sadeghi Kohan
, Sybille Hellebrand, Hans-Joachim Wunderlich:
Workload-Aware Periodic Interconnect BIST. IEEE Des. Test 41(4): 50-55 (2024)- [c223]Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich:
RAPPER: Robust and APProximate ERror Tolerating Communication. DFT 2024: 1-6 - [c222]Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. ETS 2024: 1-6 - [c221]Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. ITC 2024: 26-30 - [c220]Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Vmin Testing under Variations: Defect vs. Fault Coverage. LATS 2024: 1-6 - 2023
- [j58]Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich:
Identifying Resistive Open Defects in Embedded Cells under Variations. J. Electron. Test. 39(1): 27-40 (2023) - [c219]Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Optimizing the Streaming of Sensor Data with Approximate Communication. ATS 2023: 1-6 - [c218]Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch, Hans-Joachim Wunderlich:
Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection. DATE 2023: 1-2 - [c217]Natalia Lylina, Stefan Holst, Hanieh Jafarzadeh, Alexandra Kourfali, Hans-Joachim Wunderlich:
Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm. DSN-W 2023: 195-198 - [c216]Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich:
Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. DSN-W 2023: 203-206 - [c215]Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler:
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. ETS 2023: 1-6 - [c214]Natalia Lylina, Stefan Holst, Hanieh Jafarzadeh, Alexandra Kourfali, Hans-Joachim Wunderlich:
Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization. IOLTS 2023: 1-7 - [c213]Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Robust Pattern Generation for Small Delay Faults Under Process Variations. ITC 2023: 111-116 - [c212]Hans-Joachim Wunderlich, Hanieh Jafarzadeh, Alexandra Kourfali, Natalia Lylina, Zahra Paria Najafi-Haghi:
Test Aspects of System Health State Monitoring. LATS 2023: 1-2 - 2022
- [j57]Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich:
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks. J. Electron. Test. 38(6): 603-621 (2022) - [j56]Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich:
SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5644-5656 (2022) - [c211]Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich:
Online Periodic Test of Reconfigurable Scan Networks. ATS 2022: 78-83 - [c210]Hussam Amrouch, Jens Anders, Steffen Becker, Maik Betka, Gerd Bleher, Peter Domanski, Nourhan Elhamawy, Thomas Ertl, Athanasios Gatzastras, Paul R. Genssler, Sebastian Hasler, Martin Heinrich, André van Hoorn, Hanieh Jafarzadeh, Ingmar Kallfass, Florian Klemme, Steffen Koch, Ralf Küsters, Andrés Lalama, Raphaël Latty, Yiwen Liao, Natalia Lylina, Zahra Paria Najafi-Haghi, Dirk Pflüger, Ilia Polian, Jochen Rivoir, Matthias Sauer, Denis Schwachhofer, Steffen Templin, Christian Volmer, Stefan Wagner, Daniel Weiskopf, Hans-Joachim Wunderlich, Bin Yang, Martin Zimmermann:
Intelligent Methods for Test and Reliability. DATE 2022: 969-974 - [c209]Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich:
Robust Reconfigurable Scan Networks. DATE 2022: 1149-1152 - [c208]Zahra Paria Najafi-Haghi, Florian Klemme, Hussam Amrouch, Hans-Joachim Wunderlich:
On Extracting Reliability Information from Speed Binning. ETS 2022: 1-4 - [c207]Yiwen Liao, Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich, Bin Yang:
Efficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep Learning. ITC 2022: 185-193 - 2021
- [j55]Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich:
Stress-Aware Periodic Test of Interconnects. J. Electron. Test. 37(5): 715-728 (2021) - [c206]Chih-Hao Wang, Natalia Lylina, Ahmed Atteya, Tong-Yu Hsieh, Hans-Joachim Wunderlich:
Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. IOLTS 2021: 1-7 - [c205]Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich:
Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. ITC 2021: 20-29 - [c204]Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich:
Resistive Open Defect Classification of Embedded Cells under Variations. LATS 2021: 1-6 - [c203]Natalia Lylina, Ahmed Atteya, Hans-Joachim Wunderlich:
A Hybrid Protection Scheme for Reconfigurable Scan Networks. VTS 2021: 1-7 - 2020
- [c202]Sebastian Brandhofer, Michael A. Kochte, Hans-Joachim Wunderlich:
Synthesis of Fault-Tolerant Reconfigurable Scan Networks. DATE 2020: 798-803 - [c201]Chang Liu, Eric Schneider, Hans-Joachim Wunderlich:
Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction. DATE 2020: 804-809 - [c200]Eric Schneider, Hans-Joachim Wunderlich:
GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling. DATE 2020: 879-884 - [c199]Zahra Paria Najafi-Haghi, Marzieh Hashemipour-Nazari, Hans-Joachim Wunderlich:
Variation-Aware Defect Characterization at Cell Level. ETS 2020: 1-6 - [c198]Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen:
Logic Fault Diagnosis of Hidden Delay Defects. ITC 2020: 1-10 - [c197]Natalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich:
Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. ITC 2020: 1-10 - [c196]Eric Schneider, Hans-Joachim Wunderlich:
Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. VTS 2020: 1-6
2010 – 2019
- 2019
- [j54]Eric Schneider, Hans-Joachim Wunderlich:
Multi-level timing and fault simulation on GPUs. Integr. 64: 78-91 (2019) - [j53]Eric Schneider, Hans-Joachim Wunderlich:
SWIFT: Switch-Level Fault Simulation on GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 122-135 (2019) - [j52]Matthias Kampmann, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, Hans-Joachim Wunderlich:
Built-In Test for Hidden Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1956-1968 (2019) - [c195]Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer:
On Secure Data Flow in Reconfigurable Scan Networks. DATE 2019: 1016-1021 - [c194]Stefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich:
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. ITC 2019: 1-10 - [c193]Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich:
Security Compliance Analysis of Reconfigurable Scan Networks. ITC 2019: 1-9 - 2018
- [j51]Hans-Joachim Wunderlich, Yervant Zorian:
Guest Editor's Introduction. IEEE Des. Test 35(3): 5-6 (2018) - [j50]Michael A. Kochte, Hans-Joachim Wunderlich:
Self-Test and Diagnosis for Self-Aware Systems. IEEE Des. Test 35(5): 7-18 (2018) - [j49]Sybille Hellebrand, Jörg Henkel, Anand Raghunathan, Hans-Joachim Wunderlich:
Guest Editors' Introduction. IEEE Embed. Syst. Lett. 10(1): 1 (2018) - [c192]Eric Schneider, Michael A. Kochte, Hans-Joachim Wunderlich:
Multi-level timing simulation on GPUs. ASP-DAC 2018: 470-475 - [c191]Chang Liu, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, Hans-Joachim Wunderlich:
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. ATS 2018: 92-97 - [c190]Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian:
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. ATS 2018: 149-154 - [c189]Ahmed Atteya, Michael A. Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich:
Online prevention of security violations in reconfigurable scan networks. ETS 2018: 1-6 - [c188]Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi:
Device aging: A reliability and security concern. ETS 2018: 1-10 - [c187]Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer:
Detecting and Resolving Security Violations in Reconfigurable Scan Networks. IOLTS 2018: 91-96 - 2017
- [j48]Gert Schley, Atefe Dalirsani, Marcus Eggenberger, Nadereh Hatami, Hans-Joachim Wunderlich, Martin Radetzki:
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. IEEE Trans. Computers 66(5): 848-861 (2017) - [j47]Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jörg Henkel:
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. IEEE Trans. Computers 66(6): 957-970 (2017) - [j46]Eric Schneider, Michael A. Kochte, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich:
GPU-Accelerated Simulation of Small Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 829-841 (2017) - [c186]Dominik Ull, Michael A. Kochte, Hans-Joachim Wunderlich:
Structure-Oriented Test of Reconfigurable Scan Networks. ATS 2017: 127-132 - [c185]Michael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich:
Specification and verification of security in reconfigurable scan networks. ETS 2017: 1-6 - [c184]Marcus Wagner, Hans-Joachim Wunderlich:
Probabilistic sensitization analysis for variation-aware path delay fault test evaluation. ETS 2017: 1-6 - [c183]Alexander Schöll, Claus Braun, Hans-Joachim Wunderlich:
Energy-efficient and error-resilient iterative solvers for approximate computing. IOLTS 2017: 237-239 - [c182]Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen:
Analysis and mitigation or IR-Drop induced scan shift-errors. ITC 2017: 1-8 - [c181]Michael A. Kochte, Rafal Baranowski, Hans-Joachim Wunderlich:
Trustworthy reconfigurable access to on-chip infrastructure. ITC-Asia 2017: 119-124 - [c180]Jyotirmoy V. Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand:
Special session on early life failures. VTS 2017: 1 - [c179]Chang Liu, Michael A. Kochte, Hans-Joachim Wunderlich:
Aging monitor reuse for small delay fault testing. VTS 2017: 1-6 - 2016
- [c178]Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. ASP-DAC 2016: 749-754 - [c177]Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte:
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS 2016: 19-24 - [c176]Michael A. Kochte, Rafal Baranowski, Marcel Schaal, Hans-Joachim Wunderlich:
Test Strategies for Reconfigurable Scan Networks. ATS 2016: 113-118 - [c175]Laura Rodríguez Gómez, Hans-Joachim Wunderlich:
A Neural-Network-Based Fault Classifier. ATS 2016: 144-149 - [c174]Eric Schneider, Hans-Joachim Wunderlich:
High-Throughput Transistor-Level Fault Simulation on GPUs. ATS 2016: 150-155 - [c173]Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich:
Autonomous Testing for 3D-ICs with IEEE Std. 1687. ATS 2016: 215-220 - [c172]Atefe Dalirsani, Hans-Joachim Wunderlich:
Functional Diagnosis for Graceful Degradation of NoC Switches. ATS 2016: 246-251 - [c171]Alexander Schöll, Claus Braun, Hans-Joachim Wunderlich:
Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware. DFT 2016: 21-26 - [c170]Alexander Schöll, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich:
Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. DSN 2016: 251-262 - [c169]Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich:
Formal verification of secure reconfigurable scan network infrastructure. ETS 2016: 1-6 - [c168]Hans-Joachim Wunderlich, Peter C. Maxwell:
ETS 2015 best paper. ETS 2016: 1 - [c167]Hans-Joachim Wunderlich, Claus Braun, Alexander Schöll:
Pushing the limits: How fault tolerance extends the scope of approximate computing. IOLTS 2016: 133-136 - [c166]Michael A. Kochte, Hans-Joachim Wunderlich:
Dependable on-chip infrastructure for dependable MPSOCs. LATS 2016: 183-188 - [c165]Hans-Joachim Wunderlich, Claus Braun, Alexander Schöll:
Fault tolerance of approximate compute algorithms. VTS 2016: 1 - 2015
- [j45]Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes Maximilian Kühn, Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang:
Adaptive multi-layer techniques for increased system dependability. it Inf. Technol. 57(3): 149-158 (2015) - [j44]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Fine-Grained Access Management in Reconfigurable Scan Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 937-946 (2015) - [j43]Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2025-2038 (2015) - [j42]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation. ACM Trans. Design Autom. Electr. Syst. 20(2): 30:1-30:27 (2015) - [j41]Stefan Holst, Michael E. Imhof, Hans-Joachim Wunderlich:
High-Throughput Logic Timing Simulation on GPGPUs. ACM Trans. Design Autom. Electr. Syst. 20(3): 37:1-37:22 (2015) - [c164]Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian:
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. ATS 2015: 103-108 - [c163]Matthias Kampmann, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Optimized Selection of Frequencies for Faster-Than-at-Speed Test. ATS 2015: 109-114 - [c162]Michael A. Kochte, Atefe Dalirsani, Andrea Bernabei, Martin Omaña, Cecilia Metra, Hans-Joachim Wunderlich:
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. ATS 2015: 157-162 - [c161]Rafal Baranowski, Farshad Firouzi, Saman Kiamehr, Chang Liu, Mehdi Baradaran Tahoori, Hans-Joachim Wunderlich:
On-line prediction of NBTI-induced aging rates. DATE 2015: 589-592 - [c160]Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich:
GPU-accelerated small delay fault simulation. DATE 2015: 1174-1179 - [c159]Alexander Schöll, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich:
Low-overhead fault-tolerance for the preconditioned conjugate gradient solver. DFTS 2015: 60-65 - [c158]Hans-Joachim Wunderlich:
Testing visions. ETS 2015: 1 - [c157]Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. ICCAD 2015: 38-45 - [c156]Alexander Schöll, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich:
Efficient on-line fault-tolerance for the preconditioned conjugate gradient method. IOLTS 2015: 95-100 - [c155]Chang Liu, Michael A. Kochte, Hans-Joachim Wunderlich:
Efficient observation point selection for aging monitoring. IOLTS 2015: 176-181 - [c154]Hans-Joachim Wunderlich, Martin Radetzki:
Multi-Layer Test and Diagnosis for Dependable NoCs. NOCS 2015: 5:1-5:8 - 2014
- [j40]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j39]Laura Rodríguez Gómez, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Adaptive Bayesian Diagnosis of Intermittent Faults. J. Electron. Test. 30(5): 527-540 (2014) - [j38]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Access Port Protection for Reconfigurable Scan Networks. J. Electron. Test. 30(6): 711-723 (2014) - [j37]Sybille Hellebrand, Hans-Joachim Wunderlich:
SAT-based ATPG beyond stuck-at fault testing. it Inf. Technol. 56(4): 165-172 (2014) - [j36]Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich:
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. Microelectron. Reliab. 54(6-7): 1066-1074 (2014) - [j35]Dominik Erb, Michael A. Kochte, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker:
Exact Logic and Fault Simulation in Presence of Unknowns. ACM Trans. Design Autom. Electr. Syst. 19(3): 28:1-28:17 (2014) - [j34]Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich:
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation. ACM Trans. Design Autom. Electr. Syst. 19(4): 37:1-37:21 (2014) - [c153]Atefe Dalirsani, Nadereh Hatami, Michael E. Imhof, Marcus Eggenberger, Gert Schley, Martin Radetzki, Hans-Joachim Wunderlich:
On Covering Structural Defects in NoCs by Functional Tests. ATS 2014: 87-92 - [c152]Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich:
High Quality System Level Test and Diagnosis. ATS 2014: 298-305 - [c151]Alexander Schöll, Claus Braun, Markus Daub, Guido Schneider, Hans-Joachim Wunderlich:
Adaptive parallel simulation of a two-timescale model for apoptotic receptor-clustering on GPUs. BIBM 2014: 424-431 - [c150]Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. DAC 2014: 32:1-32:6 - [c149]Felix Reimann, Michael Glaß, Jürgen Teich, Alejandro Cook, Laura Rodríguez Gómez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein:
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. DAC 2014: 96:1-96:9 - [c148]Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich:
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. DATE 2014: 1-6 - [c147]Michael E. Imhof, Hans-Joachim Wunderlich:
Bit-Flipping Scan - A unified architecture for fault tolerance and offline test. DATE 2014: 1-6 - [c146]Claus Braun, Sebastian Halder, Hans-Joachim Wunderlich:
A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. DSN 2014: 443-454 - [c145]Alejandro Cook, Hans-Joachim Wunderlich:
Diagnosis of multiple faults with highly compacted test responses. ETS 2014: 1-6 - [c144]Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker:
Variation-aware deterministic ATPG. ETS 2014: 1-6 - [c143]Marcus Wagner, Hans-Joachim Wunderlich:
Incremental computation of delay fault detection probability for variation-aware test generation. ETS 2014: 1-6 - [c142]Eric Schneider, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich:
Data-parallel simulation for fast and accurate timing validation of CMOS circuits. ICCAD 2014: 17-23 - [c141]Atefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich:
Area-efficient synthesis of fault-secure NoC switches. IOLTS 2014: 13-18 - [c140]Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Test pattern generation in presence of unknown values based on restricted symbolic logic. ITC 2014: 1-10 - [c139]Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich:
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. ITC 2014: 1-8 - [c138]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Verifikation Rekonfigurierbarer Scan-Netze. MBMV 2014: 137-146 - [c137]Atefe Dalirsani, Michael E. Imhof, Hans-Joachim Wunderlich:
Structural Software-Based Self-Test of Network-on-Chip. VTS 2014: 1-6 - 2013
- [j33]Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
Test Strategies for Reliable Runtime Reconfigurable Architectures. IEEE Trans. Computers 62(8): 1494-1507 (2013) - [c136]Dominik Erb, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Accurate Multi-cycle ATPG in Presence of X-Values. Asian Test Symposium 2013: 245-250 - [c135]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Securing Access to Reconfigurable Scan Networks. Asian Test Symposium 2013: 295-300 - [c134]Marcus Wagner, Hans-Joachim Wunderlich:
Efficient variation-aware statistical dynamic timing analysis for delay test applications. DATE 2013: 276-281 - [c133]Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker:
Accurate QBF-based test pattern generation in presence of unknown values. DATE 2013: 436-441 - [c132]Atefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich:
SAT-based code synthesis for fault-secure circuits. DFTS 2013: 39-44 - [c131]Rafal Baranowski, Alejandro Cook, Michael E. Imhof, Chang Liu, Hans-Joachim Wunderlich:
Synthesis of workload monitors for on-line stress prediction. DFTS 2013: 137-142 - [c130]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Scan pattern retargeting and merging with reduced access time. ETS 2013: 1-7 - [c129]Hans-Joachim Wunderlich, Claus Braun, Sebastian Halder:
Efficacy and efficiency of algorithm-based fault-tolerance on GPUs. IOLTS 2013: 240-243 - [c128]Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel:
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. ITC 2013: 1-10 - 2012
- [j32]Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich:
Structural Test and Diagnosis for Graceful Degradation of NoC Switches. J. Electron. Test. 28(6): 831-841 (2012) - [j31]Michael A. Kochte, Melanie Elm, Hans-Joachim Wunderlich:
Accurate X-Propagation for Test Applications by SAT-Based Reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1908-1919 (2012) - [c127]Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Hans-Joachim Wunderlich, Jörg Henkel:
OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". AHS 2012: 38-45 - [c126]Stefan Holst, Eric Schneider, Hans-Joachim Wunderlich:
Scan Test Power Simulation on GPGPUs. Asian Test Symposium 2012: 155-160 - [c125]Alejandro Cook, Dominik Ull, Melanie Elm, Hans-Joachim Wunderlich, Helmut Randoll, Stefan Dohren:
Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Asian Test Symposium 2012: 214-219 - [c124]Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich:
Variation-Aware Fault Grading. Asian Test Symposium 2012: 344-349 - [c123]Claus Braun, Markus Daub, Alexander Schöll, Guido Schneider, Hans-Joachim Wunderlich:
Parallel simulation of apoptotic receptor-clustering on GPGPU many-core architectures. BIBM 2012: 1-6 - [c122]Alejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich:
Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. ETS 2012: 1-6 - [c121]Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich:
Efficient system-level aging prediction. ETS 2012: 1-6 - [c120]Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker:
Exact stuck-at fault classification in presence of unknowns. ETS 2012: 1-6 - [c119]Claus Braun, Stefan Holst, Hans-Joachim Wunderlich, Juan Manuel Castillo-Sanchez, Joachim Gross:
Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures. ICCD 2012: 207-212 - [c118]Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
Transparent structural online test for reconfigurable systems. IOLTS 2012: 37-42 - [c117]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Modeling, verification and pattern generation for reconfigurable scan networks. ITC 2012: 1-9 - [c116]Alejandro Cook, Sybille Hellebrand, Michael E. Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich:
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test. LATW 2012: 1-4 - [c115]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich:
A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55 - 2011
- [j30]Rafal Baranowski, Stefano Di Carlo, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Paolo Prinetto, Hans-Joachim Wunderlich, Christian G. Zoellin:
Efficient multi-level fault simulation of HW/SW systems for structural faults. Sci. China Inf. Sci. 54(9): 1784-1796 (2011) - [j29]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich:
Variation-aware fault modeling. Sci. China Inf. Sci. 54(9): 1813-1826 (2011) - [c114]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 - [c113]Abdullah Mumtaz, Michael E. Imhof, Stefan Holst, Hans-Joachim Wunderlich:
Embedded Test for Highly Accurate Defect Localization. Asian Test Symposium 2011: 213-218 - [c112]Alejandro Cook, Sybille Hellebrand, Thomas Indlekofer, Hans-Joachim Wunderlich:
Diagnostic Test of Robust Circuits. Asian Test Symposium 2011: 285-290 - [c111]Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich:
Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium 2011: 383-388 - [c110]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich:
Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78 - [c109]Michael A. Kochte, Hans-Joachim Wunderlich:
SAT-based fault coverage evaluation in the presence of unknown values. DATE 2011: 1303-1308 - [c108]Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein:
Structural In-Field Diagnosis for Random Logic Circuits. ETS 2011: 111-116 - [c107]Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich:
Structural Test for Graceful Degradation of NoC Switches. ETS 2011: 183-188 - [c106]Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell:
Towards Variation-Aware Test Methods. ETS 2011: 219-225 - [c105]Michael E. Imhof, Hans-Joachim Wunderlich:
Soft error correction in embedded storage elements. IOLTS 2011: 169-174 - [c104]Rafal Baranowski, Hans-Joachim Wunderlich:
Fail-safety in core-based system design. IOLTS 2011: 276-281 - [c103]Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich:
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38 - [c102]Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich:
P-PET: Partial pseudo-exhaustive test for high defect coverage. ITC 2011: 1-8 - 2010
- [j28]Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich:
Efficient Concurrent Self-Test with Partially Specified Patterns. J. Electron. Test. 26(5): 581-594 (2010) - [j27]Claus Braun, Hans-Joachim Wunderlich:
Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (Algorithm-based Fault-Tolerance on Many-Core Architectures). it Inf. Technol. 52(4): 209-215 (2010) - [c101]Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto:
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Asian Test Symposium 2010: 3-8 - [c100]Melanie Elm, Michael A. Kochte, Hans-Joachim Wunderlich:
On Determining the Real Output Xs by SAT-Based Reasoning. Asian Test Symposium 2010: 39-44 - [c99]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich:
Variation-Aware Fault Modeling. Asian Test Symposium 2010: 87-93 - [c98]Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin:
Efficient fault simulation on many-core processors. DAC 2010: 380-385 - [c97]Melanie Elm, Hans-Joachim Wunderlich:
BISD: Scan-based Built-In self-diagnosis. DATE 2010: 1243-1248 - [c96]Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich:
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. DSN Workshops 2010: 95-100 - [c95]Claus Braun, Hans-Joachim Wunderlich:
Algorithm-based fault tolerance for many-core architectures. ETS 2010: 253 - [c94]Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto:
System reliability evaluation using concurrent multi-level simulation of structural faults. ITC 2010: 817 - [c93]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 - [c92]Christian G. Zoellin, Hans-Joachim Wunderlich:
Low-power test planning for arbitrary at-speed delay-test clock schemes. VTS 2010: 93-98
2000 – 2009
- 2009
- [j26]Stefan Holst, Hans-Joachim Wunderlich:
Adaptive Debug and Diagnosis Without Fault Dictionaries. J. Electron. Test. 25(4-5): 259-268 (2009) - [c91]Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto:
Test exploration and validation using transaction level models. DATE 2009: 1250-1253 - [c90]Stefan Holst, Hans-Joachim Wunderlich:
A diagnosis algorithm for extreme space compaction. DATE 2009: 1355-1360 - [c89]Hans-Joachim Wunderlich:
Software-Based Hardware Fault Tolerance for Many-Core Architectures. DFT 2009: 223-223 - [c88]Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich:
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. ETS 2009: 53-58 - [c87]Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich:
Test Encoding for Extreme Response Compaction. ETS 2009: 155-160 - [c86]Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz:
Restrict Encoding for Mixed-Mode BIST. VTS 2009: 179-184 - 2008
- [c85]Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding:
Scan chain clustering for test power reduction. DAC 2008: 828-833 - [c84]Melanie Elm, Hans-Joachim Wunderlich:
Scan Chain Organization for Embedded Diagnosis. DATE 2008: 468-473 - [c83]Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich:
Test Set Stripping Limiting the Maximum Number of Specified Bits. DELTA 2008: 581-586 - [c82]Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker:
Selective Hardening in Early Design Steps. ETS 2008: 185-190 - [c81]Stefan Holst, Hans-Joachim Wunderlich:
Adaptive Debug and Diagnosis without Fault Dictionaries. ETS 2008: 199-204 - [c80]Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin:
Integrating Scan Design and Soft Error Correction in Low-Power Applications. IOLTS 2008: 59-64 - [c79]Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich:
Signature Rollback - A Technique for Testing Robust Circuits. VTS 2008: 125-130 - 2007
- [j25]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic logic BIST for transition fault testing. IET Comput. Digit. Tech. 1(3): 180-186 (2007) - [c78]Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
Scan Test Planning for Power Reduction. DAC 2007: 521-526 - [c77]Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. DDECS 2007: 185-190 - [c76]Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube:
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. DFT 2007: 50-58 - [c75]Stefan Holst, Hans-Joachim Wunderlich:
Adaptive Debug and Diagnosis without Fault Dictionaries. ETS 2007: 7-12 - [c74]Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. ETS 2007: 91-96 - [c73]Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers:
Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI 2007: 287-292 - [c72]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef:
Programmable deterministic Built-In Self-Test. ITC 2007: 1-9 - 2006
- [j24]Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich:
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). it Inf. Technol. 48(5): 304- (2006) - [j23]Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke:
X-masking during logic BIST and its impact on defect coverage. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 193-202 (2006) - [c71]Jun Zhou, Hans-Joachim Wunderlich:
Software-based self-test of processors under power constraints. DATE 2006: 430-435 - [c70]Talal Arnaout, Gunter Bartsch, Hans-Joachim Wunderlich:
Some Common Aspects of Design Validation, Debug and Diagnosis. DELTA 2006: 3-10 - [c69]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers:
Deterministic Logic BIST for Transition Fault Testing. ETS 2006: 123-130 - [c68]Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. ITC 2006: 1-8 - [c67]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408 - 2005
- [c66]Hans-Joachim Wunderlich:
From embedded test to embedded diagnosis. ETS 2005: 216-221 - [c65]Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich:
On the Reliability Evaluation of SRAM-Based FPGA Designs. FPL 2005: 403-408 - [c64]Jun Zhou, Hans-Joachim Wunderlich:
Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. GI Jahrestagung (1) 2005: 441 - [c63]Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rainer Dorsch, Hans-Joachim Wunderlich:
Development of an audio player as system-on-a-chip using an open source platform. ISCAS (3) 2005: 2935-2938 - [c62]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel:
Implementing a Scheme for External Deterministic Self-Test. VTS 2005: 101-106 - 2004
- [j22]Hans-Joachim Wunderlich, Sandeep K. Shukla:
Panel Summaries. IEEE Des. Test Comput. 21(1): 65-66 (2004) - [c61]Talal Arnaout, Peter Göhner, Hans-Joachim Wunderlich, Eduard Zimmer:
Reliability Considerations forMechatronic Systems on the Basis of a State Model. ARCS Workshops 2004: 106-112 - [c60]Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich:
Impact of Test Point Insertion on Silicon Area and Timing during Layout. DATE 2004: 810-815 - [c59]Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich:
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA 2004: 135-139 - [c58]Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST. ITC 2004: 48-56 - [c57]Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451 - 2003
- [j21]Shishpal Rawat, Hans-Joachim Wunderlich:
Introduction. ACM Trans. Design Autom. Electr. Syst. 8(4): 397-398 (2003) - [c56]Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86 - 2002
- [j20]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. 19(5): 44-52 (2002) - [j19]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. J. Electron. Test. 18(2): 159-170 (2002) - [j18]Rainer Dorsch, Hans-Joachim Wunderlich:
Reusing Scan Chains for Test Pattern Decompression. J. Electron. Test. 18(2): 231-240 (2002) - [j17]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
A Mixed-Mode BIST Scheme Based on Folding Compression. J. Comput. Sci. Technol. 17(2): 203-212 (2002) - [j16]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
Efficient Online and Offline Testing of Embedded DRAMs. IEEE Trans. Computers 51(7): 801-809 (2002) - [c55]Lars Schäfer, Rainer Dorsch, Hans-Joachim Wunderlich:
RESPIN++ - deterministic embedded test. ETW 2002: 37-44 - [c54]Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich:
Combining deterministic logic BIST with test point insertion. ETW 2002: 105-110 - [c53]Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer:
Adapting an SoC to ATE Concurrent Test Capabilities. ITC 2002: 1169-1175 - 2001
- [j15]Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich:
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. J. Electron. Test. 17(3-4): 341-349 (2001) - [j14]Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich:
Application of Deterministic Logic BIST on Industrial Circuits. J. Electron. Test. 17(3-4): 351-362 (2001) - [c52]Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich:
Circuit partitioning for efficient logic BIST synthesis. DATE 2001: 86-91 - [c51]Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich:
On applying the set covering model to reseeding. DATE 2001: 156-161 - [c50]Rainer Dorsch, Hans-Joachim Wunderlich:
Using mission logic for embedded testing. DATE 2001: 805 - [c49]Rainer Dorsch, Hans-Joachim Wunderlich:
Reusing scan chains for test pattern decompression. ETW 2001: 124-132 - [c48]Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich:
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469 - [c47]Rainer Dorsch, Hans-Joachim Wunderlich:
Tailoring ATPG for embedded testing. ITC 2001: 530-537 - [c46]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
Two-dimensional test data compression for scan-based deterministic BIST. ITC 2001: 894-902 - [c45]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311 - 2000
- [j13]Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with Partial Scan. J. Electron. Test. 16(3): 169-177 (2000) - [j12]Stefan Gerstendörfer, Hans-Joachim Wunderlich:
Minimized Power Consumption for Scan-Based BIST. J. Electron. Test. 16(3): 203-212 (2000) - [c44]Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich:
Optimal Hardware Pattern Generation for Functional BIST. DATE 2000: 292-297 - [c43]Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen:
Application of deterministic logic BIST on industrial circuits. ITC 2000: 105-114 - [c42]Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich:
Non-intrusive BIST for systems-on-a-chip. ITC 2000: 644-651 - [c41]Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang:
A mixed mode BIST scheme based on reseeding of folding counters. ITC 2000: 778-784
1990 – 1999
- 1999
- [j11]Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with Multiple Scan Chains. J. Electron. Test. 14(1-2): 85-93 (1999) - [c40]Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik:
Symmetric Transparent BIST for RAMs. DATE 1999: 702-707 - [c39]Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich:
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. EDCC 1999: 339-350 - [c38]Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with partial scan. ETW 1999: 110-116 - [c37]Stefan Gerstendörfer, Hans-Joachim Wunderlich:
Minimized power consumption for scan-based BIST. ITC 1999: 77-84 - [c36]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik:
Error Detecting Refreshment for Embedded DRAMs. VTS 1999: 384-390 - 1998
- [j10]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig:
Synthesizing Fast, Online-Testable Control Units. IEEE Des. Test Comput. 15(4): 36-41 (1998) - [j9]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig:
Mixed-Mode BIST Using Embedded Processors. J. Electron. Test. 12(1-2): 127-138 (1998) - [j8]Hans-Joachim Wunderlich:
BIST for systems-on-a-chip. Integr. 26(1-2): 55-78 (1998) - [j7]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Hardware-optimal test register insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 531-539 (1998) - [c35]Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich:
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Asian Test Symposium 1998: 492-499 - [c34]Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich:
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. DATE 1998: 173-179 - [c33]Rainer Dorsch, Hans-Joachim Wunderlich:
Accumulator based deterministic BIST. ITC 1998: 412-421 - [c32]Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with multiple scan chains. ITC 1998: 1057-1064 - [c31]Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich:
Fast Self-Recovering Controllers. VTS 1998: 296-302 - 1997
- [j6]Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich:
Guest Editorial. J. Electron. Test. 11(1): 7-8 (1997) - [c30]Andre Hertwig, Hans-Joachim Wunderlich:
Fast controllers for data dominated applications. ED&TC 1997: 84-89 - [c29]Gundolf Kiefer, Hans-Joachim Wunderlich:
Using BIST Control for Pattern Generation. ITC 1997: 347-355 - [c28]Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457 - 1996
- [c27]Birgit Reeb, Hans-Joachim Wunderlich:
Deterministic Pattern Generation for Weighted Random Pattern Testing. ED&TC 1996: 30-36 - [c26]Hans-Joachim Wunderlich, Gundolf Kiefer:
Bit-flipping BIST. ICCAD 1996: 337-343 - [c25]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig:
Mixed-Mode BIST Using Embedded Processors. ITC 1996: 195-204 - 1995
- [c24]Hans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Calderón:
Synthesis of IDDQ-testable circuits: integrating built-in current sensors. ED&TC 1995: 573-580 - [c23]Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich:
Pattern generation for a deterministic BIST scheme. ICCAD 1995: 88-94 - [c22]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Test register insertion with minimum hardware cost. ICCAD 1995: 95-101 - 1994
- [c21]Sybille Hellebrand, Hans-Joachim Wunderlich:
Synthesis of Self-Testable Controllers. EDAC-ETC-EUROASIC 1994: 580-585 - [c20]Sybille Hellebrand, Hans-Joachim Wunderlich:
An efficient procedure for the synthesis of fast self-testable controller structures. ICCAD 1994: 110-116 - [c19]Olaf Stern, Hans-Joachim Wunderlich:
Simulation Results of an Efficient Defect-Analysis Procedure. ITC 1994: 729-738 - [c18]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Configuring Flip-Flops to BIST Registers. ITC 1994: 939-948 - 1992
- [j5]Hans-Joachim Wunderlich, Michael H. Schulz:
Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. Inform. Spektrum 15(1): 23-32 (1992) - [j4]Hans-Joachim Wunderlich, Sybille Hellebrand:
The pseudoexhaustive test of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1): 26-33 (1992) - [j3]Bernhard Eschermann, Hans-Joachim Wunderlich:
Optimized synthesis techniques for testable sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3): 301-312 (1992) - 1991
- [c17]Bernhard Eschermann, Hans-Joachim Wunderlich:
A Unified Approach for the Synthesis of Self-Testable Finite State Machines. DAC 1991: 372-377 - [c16]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Signature Analysis and Test Scheduling for Self-Testable Circuits. FTCS 1991: 96-103 - [c15]Bernhard Eschermann, Hans-Joachim Wunderlich:
Emulation of Scan Paths in Sequential Circuit Synthesis. Fault-Tolerant Computing Systems 1991: 136-147 - [c14]Thomas Kropf, Hans-Joachim Wunderlich:
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. ITC 1991: 57-66 - 1990
- [j2]Arno Kunzmann, Hans-Joachim Wunderlich:
An analytical approach to the partial scan problem. J. Electron. Test. 1(2): 163-174 (1990) - [j1]Hans-Joachim Wunderlich:
Multiple distributions for biased random test patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 584-593 (1990) - [c13]Sybille Hellebrand, Hans-Joachim Wunderlich:
Tools and devices supporting the pseudo-exhaustive test. EURO-DAC 1990: 13-17 - [c12]Peter C. Maxwell, Hans-Joachim Wunderlich:
The effectiveness of different test sets for PLAs. EURO-DAC 1990: 628-632 - [c11]Bernhard Eschermann, Hans-Joachim Wunderlich:
Optimized synthesis of self-testable finite state machines. FTCS 1990: 390-397 - [c10]Albrecht P. Stroele, Hans-Joachim Wunderlich:
Error masking in self-testable circuits. ITC 1990: 544-552 - [c9]Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl:
Generating pseudo-exhaustive vectors for external testing. ITC 1990: 670-679
1980 – 1989
- 1989
- [c8]Hans-Joachim Wunderlich:
The design of random-testable sequential circuits. FTCS 1989: 110-117 - [c7]Sybille Hellebrand, Hans-Joachim Wunderlich:
The Pseudo-Exhaustive Test of Sequential Circuits. ITC 1989: 19-27 - 1988
- [c6]Hans-Joachim Wunderlich, Sybille Hellebrand:
Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits. FTCS 1988: 36-41 - [c5]Sybille Hellebrand, Hans-Joachim Wunderlich:
Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI Jahrestagung (2) 1988: 145-159 - [c4]Hans-Joachim Wunderlich:
Multiple Distributions for Biased Random Test Patterns. ITC 1988: 236-244 - 1987
- [b1]Hans-Joachim Wunderlich:
Probabilistische Verfahren für den Test hochintegrierter Schaltungen. Karlsruhe Institute of Technology, Germany, Informatik-Fachberichte 140, Springer 1987, ISBN 3-540-18072-9, pp. 1-133 - [c3]Hans-Joachim Wunderlich:
On Computing Optimized Input Probabilities for Random Tests. DAC 1987: 392-398 - 1986
- [c2]Hans-Joachim Wunderlich, Wolfgang Rosenstiel:
On fault modeling for dynamic MOS circuits. DAC 1986: 540-546 - 1985
- [c1]Hans-Joachim Wunderlich:
PROTEST: a tool for probabilistic testability analysis. DAC 1985: 204-211
Coauthor Index
[j59] [c223] [c222] [c221] [c220] [c219] [c216] [c213] [j55] [c198] [j52] [j49] [c191] [c180] [c163] [j39] [j37] [c139] [c122] [c116] [j29] [c112] [c106] [c99] [c96] [c79] [c77] [c76] [c74] [j24] [j19] [j17] [j16] [j15] [c46] [c41] [c40] [c39] [c36] [j10] [j9] [c34] [c31] [c25] [c23] [c21] [c20] [j4] [c13] [c9] [c7] [c6] [c5]
[c202] [j52] [c194] [j50] [c192] [c189] [c187] [j47] [j46] [c186] [c185] [c182] [c181] [c179] [c178] [c177] [c176] [c173] [c170] [c169] [c166] [j45] [j44] [j43] [j42] [c164] [c163] [c162] [c160] [c159] [c157] [c156] [c155] [j38] [j36] [j35] [c150] [c141] [c140] [c139] [c138] [j33] [c136] [c135] [c133] [c132] [c130] [c128] [j31] [c127] [c120] [c118] [c117] [j30] [c111] [c109] [c103] [j28] [c101] [c100] [c98] [c94] [c91] [c88] [c87] [c83]
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