default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 2014: Seattle, WA, USA
- 2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-4722-5
- Michael Purtell, Subhasish Mitra:
Welcome message. 1-2
Session 1 - What new defects will new technologies bring?
- Paul G. Ryan, Irfan Aziz, William B. Howell, Teresa K. Janczak, Davia J. Lu:
Process defect trends and strategic test gaps. 1-8 - Chao Han, Adit D. Singh:
On the testing of hazard activated open defects. 1-6 - J. K. Jerry Lee, Amr Haggag, William Eklow:
Protecting against emerging vmin failures in advanced technology nodes. 1-7
Session 2 - Modeling and measuring complex analog behaviours
- Nicholas Tzou, Debesh Bhatta, Abhijit Chatterjee:
Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signals. 1-10 - Mani Soma:
Analog fault models: Back to the future? 1 - Stephen Sunter, Krzysztof Jurga, Peter Dingenen, Ronny Vanhooren:
Practical random sampling of potential defects for analog fault simulation. 1-10
Session 3 - Security: From chips to the Internet of Things
- Steve Trimberger:
Security solutions in the first-generation Zynq All-Programmable SoC. 1 - Bill Curtis:
Delivering security by design in the Internet of Things. 1 - Pradip Bose:
Energy-secure computer architectures. 1
Session 4 - Robust energy systems
- Mani Vadari:
Dynamic microgrids - A potential solution for enhanced resiliency in distribution systems. 1 - Kevin Schneider:
Microgrids as a resiliency resource. 1 - Alexandra von Meier:
Recruiting distributed resources for grid resilience: The need for transparency. 1
Session 5 - Discussion session: Has adaptive test lived up to its expectations?
- Carl Bowen:
Concerns over predictability of supply and quality. 1 - Stacy Ajouri:
The desire-friction ratio of Adaptive test. 1 - Wesley Smith:
Collaboration and teamwork obstacles. 1 - Mark Roos:
ATE and test equipment vendors; Hardware not software. 1
Session 6 - More test compression: Cadence, Mentor, Synopsys
- Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen:
Efficient testing of hierarchical core-based SOCs. 1-10 - Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. 1-7 - Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane:
Achieving extreme scan compression for SoC Designs. 1-8
Session 7 - Tackling timing and power during test
- John Schulze, Ryan Tally:
Mitigating voltage droop during scan with variable shift frequency. 1-8 - Raashid Shaikh, Pradeep Wilson, Khushboo Agarwal, H. V. Sanjay, Rajesh Tiwari, Kaushik Lath, Srivaths Ravi:
At-speed capture power reduction using layout-aware granular clock gate enable controls. 1-10 - Stephen Sunter, Saghir A. Shaikh, Qing Lin:
Fast BIST of I/O Pin AC specifications and inter-chip delays. 1-8
Session 8 - Learn from the experts: High volume manufacturing
- Andreas Kux, Rudolf Ullmann, Thomas Kern, Roland Strunz, Hanno Melzner, Stephan Beuven, Andreas Haase:
Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screening. 1-7 - Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada:
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. 1-10 - Sajjad Pagarkar:
Challenges of testing 100M chips. 1
Session 9 - RF Test: Digital ate, radios, radars
- Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
Low-cost phase noise testing of complex RF ICs using standard digital ATE. 1-9 - Brian A. Floyd
:
Market opportunities and testing challenges for millimeter-wave radios and radars. 1 - Chun-Hsien Peng, ChiaYu Yang, Adonis Tsu, Chung-Jin Tsai, Yosen Chen, C.-Y. Lin, Kai Hong, Kaipon Kao, Paul C. P. Liang, Chao Long Tsai, Charles Chien, H. C. Hwang:
A novel RF self test for a combo SoC on digital ATE with multi-site applications. 1-8
Session 10 - "Fool" nyquist, fix nonlinearity, tolerate jitter
- Fumitaka Abe, Yutaro Kobayashi, Kenji Sawada, Keisuke Kato, Osamu Kobayashi, Haruo Kobayashi:
Low-distortion signal generation for ADC testing. 1-10 - Myeong-Jae Park, Jaeha Kim:
A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers. 1-6 - Boris Murmann:
Teaching an old dog new tricks: Views on the future of mixed-signal IC design. 1
Session 11 - Embedded systems: From firmware to large-scale applications
- Praveen K. Murthy:
Top ten challenges in Big Data security and privacy. 1 - Carlos Villarraga, Bernard Schmidt, Binghao Bao, Rakesh Raman, Christian Bartsch, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz:
Software in a hardware view: New models for HW-dependent software in SoC verification and test. 1-9 - Guillaume Brat:
Compositional verification using formal analysis for a flight critical system. 1
Session 12 - Test enables technology bringup
- Greg Yeric:
Design, technology and yield in the post-moore era. 1 - Saman Adham, Jonathan Chang, Hung-Jen Liao, John Hung, Ting-Hua Hsieh:
The importance of DFX, a foundry perspective. 1-6 - Yue Liang:
Yield and performance improvement through technology-design co-optimization in advanced technology nodes. 1
Session 14 - Advances in packaging and probing
- Madhavan Swaminathan:
Managing signal, power and thermal integrity for 3D integration. 1 - Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui:
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface. 1-10 - Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Wafer Level Chip Scale Package copper pillar probing. 1-6
Session 15 - Building robust systems: Under test and in the wild
- Bianca Schroeder:
A tale of two lives: Under test and in the wild. 1 - Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam:
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation. 1-6 - Hyeran Jeon, Gabriel H. Loh, Murali Annavaram:
Efficient RAS support for die-stacked DRAM. 1-10
Session 16 - Emerging SOS challenges
- Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji:
Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. 1-9 - Bong Hyun Lee:
Thermal-aware mobile SoC design and test in 14nm finfet technology. 1 - Farrokh Ghani Zadegan, Gunnar Carlsson, Erik Larsson:
Robustness of TAP-based scan networks. 1-10
Session 17 - Coding, coverage, vmin, and repair: Tradeoffs in today's embedded memories
- Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine:
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. 1 - Yervant Zorian:
Design, test & repair methodology for FinFET-based memories. 1 - Harsharaj Ellur, Kalpesh Shah:
A Tag based solution for efficient utilization of efuse for memory repair. 1-7
Session 18 - Big data: Big problem or opportunity for test?
- Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris:
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. 1-10 - Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
Yield optimization using advanced statistical correlation methods. 1-10 - Anne Gattiker:
Big data and test. 1
Session 19 - Statistical apporaches to AMS design and test
- Constantinos Xanthopoulos, Ke Huang, Abbas Poonawala, Amit Nahar, Bob Orr, John M. Carulli Jr., Yiorgos Makris:
IC laser trimming speed-up through wafer-level spatial correlation modeling. 1-7 - Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Baris Esen:
Design and test of analog circuits towards sub-ppm level. 1-2
Session 20 - Test and yield go 3-D
- Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Redundancy architectures for channel-based 3D DRAM yield improvement. 1-7 - Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr:
Vesuvius-3D: A 3D-DfT demonstrator. 1-10 - Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow:
A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs. 1-10
Session 21 - Boards and test: Not your dad's board test
- T. M. Mak:
Interposer test: Testing PCBs that have shrunk 100x. 1 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu:
Knowledge discovery and knowledge transfer in board-level functional fault diagnosis. 1-10 - C. Glenn Shirley, W. Robert Daasch, Phil Nigh, Zoe Conroy:
Board manufacturing test correlation to IC manufacturing test. 1-8
Session 22 - Validation: Pre-silicon, emulation, post-silicon
- Xiaobing Shi, Nicola Nicolici:
On-chip constrained random stimuli generation for post-silicon validation using compact masks. 1-10 - Kenneth Larsen:
Emulation and its connection to test. 1 - Zissis Poulos, Andreas G. Veneris:
Clustering-based failure triage for RTL regression debugging. 1-10
Session 23 - RAM test and repair: Today and tomorrow
- Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang:
A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time. 1-10 - Raphael Robertazzi, Janusz Nowak, Jonathan Sun:
Analytical MRAM test. 1-10 - Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Read disturb fault detection in STT-MRAM. 1-7
Session 24 - Connecting process variation, yield, and diagnosis
- Youngok K. Pino, Vinayaka Jyothi, Matthew French:
Intra-die process variation aware anomaly detection in FPGAs. 1-6 - Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng:
Feature engineering with canonical analysis for effective statistical tests screening test escapes. 1-10 - Ronald D. Blanton, Ben Niewenhuis, Carl Taylor:
Logic characterization vehicle design for maximal information extraction for yield learning. 1-10
Session 25 - Functional testing: A fresh look
- Harry H. Chen:
The case for analyzing system level failures using structural patterns. 1 - Shahrzad Mirkhani, Jacob A. Abraham:
EAGLE: A regression model for fault coverage estimation using a simulation based metric. 1-10 - Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick:
Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns. 1-8
Session 26 - Think you know ATPG? Think again
- X. Cai, Peter Wohl, Daniel Martin:
Fault sharing in a copy-on-write based ATPG system. 1-8 - Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Test pattern generation in presence of unknown values based on restricted symbolic logic. 1-10 - Masahiro Fujita, Alan Mishchenko:
Efficient SAT-based ATPG techniques for all multiple stuck-at faults. 1-10
Session 27 - Stay "tuned" for analog testing
- Y. Fan, A. Verma, J. Janney, S. Kumar:
Testing silicon TV tuners on ATE without TV signal generator. 1-9 - Xian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee:
A self-tuning architecture for buck converters based on alternative test. 1-10 - Li Xu, Degang Chen:
Fast co-test of linearity and spectral performance with non-coherent sampled and amplitude clipped data. 1-8
Session 28 - Attacks and countermeasures for secure chips
- Jennifer Dworak, Zoe Conroy, Alfred L. Crouch, John C. Potter:
Board security enhancement using new locking SIB-based architectures. 1-10 - Peilin Song, Franco Stellari, Alan J. Weger:
Counterfeit IC detection using light emission. 1-8 - Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri:
Test-mode-only scan attack and countermeasure for contemporary scan architectures. 1-8
Session 29 - Logic test compression + logic bist
- Sreenivaas S. Muthyala, Nur A. Touba:
Improving test compression with scan feedforward techniques. 1-10 - Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao:
A diagnosis-friendly LBIST architecture with property checking. 1-9 - Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich:
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. 1-8
Session 30 - What's wrong with my chip?
- Kuen-Jong Lee, Cheng-Hung Wu:
An efficient diagnosis-aware pattern generation procedure for transition faults. 1-10 - Shih-Min Chao, Po-Juei Chen, Jing-Yu Chen, Po-Hao Chen, Ang-Feng Lin, James Chien-Mo Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li:
Divide and conquer diagnosis for multiple defects. 1-8 - Sergej Deutsch, Krishnendu Chakrabarty:
Massive signal tracing using on-chip DRAM for in-system silicon debug. 1-10
IEEE TTTC E. J. McCluskey Doctoral Dissertation Competition: Final Round
- Julio Vazquez Hernandez:
Error prediction and detection methodologies for reliable circuit operation under NBTI. 1-10 - Samah Mohamed Saeed:
DfST: Design for secure testability. 1-10 - Luca Cassano:
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs. 1-10 - Rashid Rashidzadeh, Iftekhar Ibne Basith:
A test probe for TSV using resonant inductive coupling. 1-10 - Da Cheng, Sandeep K. Gupta:
Optimizing redundancy design for chip-multiprocessors for flexible utility functions. 1-8 - Shanghang Zhang, Xin Li, Ronald D. Blanton, José Machado da Silva, John M. Carulli Jr., Kenneth M. Butler:
Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling. 1-10
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-11 21:37 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
