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2020 – today
- 2022
[j70]Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada:
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. 105-C(10): 544-551 (2022)- 2021
- [c135]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada:
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT 2021: 1-4
2010 – 2019
- 2019
- [j69]Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada:
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16(19): 20190390 (2019) - [j68]Daigo Takahashi
, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68(7): 2519-2530 (2019) - [j67]Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 11-19 (2019) - 2018
- [j66]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34(2): 147-161 (2018) - [j65]Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda:
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15(5) (2018) - [j64]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 410-424 (2018) - [j63]Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada:
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. 101-C(4): 218-223 (2018) - [j62]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. 101-C(4): 292-298 (2018) - [j61]Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada:
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. 67(4): 745-753 (2018) - [c134]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS 2018: 408-411 - [c133]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) 2018: 1-13 - [c132]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC 2018: 55-58 - 2017
- [j60]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 200-209 (2017) - [j59]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. 100-C(9): 736-745 (2017) - [j58]Nguyen Ngoc Mai Khanh, Kunihiro Asada:
A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications. IEICE Trans. Electron. 100-C(12): 1078-1086 (2017) - [j57]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2741-2749 (2017) - [c131]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC 2017: 23-24 - [c130]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
CMOS-on-quartz pulse generator for low power applications. ASP-DAC 2017: 29-30 - [c129]Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging 2017: 18-23 - [c128]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS 2017: 1-2 - [c127]Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS 2017: 1-4 - [c126]Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS 2017: 231-234 - [c125]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS 2017: 318-321 - [c124]Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada:
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS 2017: 1-3 - [c123]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS 2017: 257-260 - 2016
- [j56]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. J. Electron. Test. 32(3): 257-271 (2016) - [j55]Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada:
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. IEICE Trans. Electron. 99-C(2): 275-284 (2016) - [j54]Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. IEICE Trans. Electron. 99-C(10): 1219-1225 (2016) - [j53]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25(3): 1640017:1-1640017:16 (2016) - [c122]Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC 2016: 313-316 - [c121]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE 2016: 517-522 - [c120]Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada:
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC 2016: 301-304 - [c119]Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada:
One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. EWME 2016: 1-3 - [c118]Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS 2016: 29-32 - [c117]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Resonant power supply noise reduction using a triangular active charge injection. ICECS 2016: 113-116 - [c116]Masahiro Kano, Toru Nakura, Kunihiro Asada:
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. ISQED 2016: 386-391 - [c115]Toru Nakura, Kunihiro Asada:
Fully automated PLL compiler generating final GDS from specification. ISQED 2016: 437-442 - [c114]Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC 2016: 1-8 - [c113]James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada:
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS 2016: 1-4 - 2015
- [j52]Toru Nakura, Hiroaki Matsui, Kunihiro Asada:
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. IEICE Electron. Express 12(3): 20141114 (2015) - [j51]Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada:
Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. IEICE Trans. Electron. 98-C(7): 734-740 (2015) - [j50]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. 64(4): 840-848 (2015) - [c112]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC 2015: 1-4 - [c111]Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada:
A Technique for Analyzing On-Chip Power Supply Impedance. ATS 2015: 193-198 - [c110]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS 2015: 131-136 - [c109]Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS 2015: 1-4 - 2014
- [j49]Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada:
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 777-780 (2014) - [j48]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1688-1698 (2014) - [c108]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS 2014: 168-173 - [c107]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Burst-pulse Generator based on transmission line toward sub-MMW. DDECS 2014: 59-64 - [c106]Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada:
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. DDECS 2014: 282-285 - [c105]Toru Nakura, Kunihiro Asada:
Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. EWME 2014: 133-136 - [c104]Hongbo Zhu, Kunihiro Asada:
A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique. ICECS 2014: 363-366 - [c103]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS 2014: 93-96 - [c102]Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada:
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. ITC 2014: 1-10 - [c101]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS 2014: 111-114 - 2013
- [j47]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Trans. Electron. 96-C(4): 518-527 (2013) - [j46]Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. IEICE Trans. Electron. 96-C(4): 560-567 (2013) - [j45]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2458-2466 (2013) - [c100]Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC 2013: 255-260 - [c99]Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada:
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC 2013: 1-4 - [c98]Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC 2013: 1-4 - [c97]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC 2013: 1-4 - [c96]Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Pulse Width controlled PLL and its automated design flow. ICECS 2013: 5-8 - [c95]Tomohiko Yano, Toru Nakura, Kunihiro Asada:
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. ICECS 2013: 625-628 - [c94]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD 2013: 69-76 - [c93]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC 2013: 1-8 - 2012
- [j44]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS. IEICE Electron. Express 9(12): 1057-1061 (2012) - [j43]Toru Nakura, Kunihiro Asada:
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. IEICE Trans. Electron. 95-C(2): 297-302 (2012) - [j42]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Trans. Electron. 95-C(4): 546-554 (2012) - [j41]Tetsuya Iizuka, Kunihiro Asada:
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. 95-C(4): 627-634 (2012) - [j40]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Trans. Electron. 95-C(4): 643-650 (2012) - [j39]Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada:
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. 95-C(4): 661-667 (2012) - [j38]Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. 95-C(12): 1857-1863 (2012) - [j37]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2234-2241 (2012) - [c92]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC 2012: 150-157 - [c91]Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira:
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium 2012: 185-190 - [c90]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium 2012: 252-257 - [c89]Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada:
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC 2012: 1-4 - [c88]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. COOL Chips 2012: 1-3 - [c87]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
Range extension of inductive coupling communication using multi-stage resonance. ISCIT 2012: 758-763 - [c86]James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada:
A design-for-test apparatus for measuring on-chip temperature with fine granularity. ISQED 2012: 27-32 - [c85]Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power integrity control of ATE for emulating power supply fluctuations on customer environment. ITC 2012: 1-10 - 2011
- [j36]Tetsuya Iizuka, Kunihiro Asada:
All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express 8(1): 20-25 (2011) - [j35]Shingo Mandai, Taihei Momma, Makoto Ikeda, Kunihiro Asada:
Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. IEICE Trans. Electron. 94-C(1): 124-127 (2011) - [j34]Salih Ergün, Ülkühan Güler, Kunihiro Asada:
A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 180-190 (2011) - [j33]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. 94-C(4): 487-494 (2011) - [j32]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Trans. Electron. 94-C(4): 511-519 (2011) - [j31]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability. IEICE Trans. Electron. 94-C(4): 627-634 (2011) - [j30]Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. 94-C(4): 654-662 (2011) - [j29]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. 94-C(6): 1098-1104 (2011) - [j28]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging. IEICE Trans. Electron. 94-C(10): 1626-1633 (2011) - [j27]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2554-2562 (2011) - [j26]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. J. Next Gener. Inf. Technol. 2(4): 1-9 (2011) - [j25]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. IEEE J. Solid State Circuits 46(11): 2500-2513 (2011) - [c84]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76 - [c83]Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80 - [c82]Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada:
A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS. ASP-DAC 2011: 107-108 - [c81]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114 - [c80]Tetsuya Iizuka, Kunihiro Asada:
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS 2011: 115-120 - [c79]Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada:
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186 - [c78]Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada:
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC 2011: 399-402 - [c77]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS 2011: 53-56 - [c76]Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS 2011: 220-223 - [c75]Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada:
All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS 2011: 607-610 - [c74]Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada:
An equivalent-time and clocked approach for continuous-time quantization. ISCAS 2011: 2529-2532 - [c73]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED 2011: 3-8 - [c72]Teruki Nakasato, Toru Nakura, Kunihiro Asada:
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. ISOCC 2011: 150-153 - [c71]Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu:
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC 2011: 1-10 - 2010
- [j24]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A 8bit two stage time-to-digital converter using time difference amplifier. IEICE Electron. Express 7(13): 943-948 (2010) - [j23]Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada:
Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Trans. Electron. 93-C(3): 303-308 (2010) - [j22]Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1319-1328 (2010) - [c70]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Cascaded time difference amplifier using differential logic delay cell. ASP-DAC 2010: 355-356 - [c69]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. DATE 2010: 1755-1760 - [c68]Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172 - [c67]Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe:
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. DFT 2010: 3 - [c66]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC 2010: 182-185 - [c65]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC 2010: 266-269 - [c64]Shingo Mandai, Makoto Ikeda, Kunihiro Asada:
A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. ISSCC 2010: 404-405
2000 – 2009
- 2009
- [j21]Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Trans. Electron. 92-C(6): 798-805 (2009) - [c63]Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada:
Circuit design using stripe-shaped PMELA TFTs on glass. ASP-DAC 2009: 105-106 - [c62]Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda:
Measurement of power supply noise tolerance of self-timed processor. DDECS 2009: 128-131 - [c61]Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209 - [c60]Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada:
SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD 2009: 643-646 - [c59]Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC 2009: 156-159 - [c58]Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. ETS 2009: 107-112 - [c57]MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI 2009: 177-180 - 2007
- [j20]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 716-720 (2007) - [c56]Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC 2007: 100-101 - [c55]Zhicheng Liang, Makoto Ikeda, Kunihiro Asada:
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. DDECS 2007: 81-86 - [c54]Yusuke Yachide, Makoto Ikeda, Kunihiro Asada:
FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method. FPT 2007: 293-296 - [c53]Makoto Ikeda, Ken Ishii, Taku Sogabe, Kunihiro Asada:
Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS. ICECS 2007: 154-157 - [c52]Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada:
3.5-Gb/s extended frequency range wave-pipeline PRBS Generator in 0.18-μm CMOS. ICECS 2007: 526-529 - [c51]Kenichiro Kurihara, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. ICECS 2007: 1296-1299 - [c50]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED 2007: 776-781 - [c49]Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada:
LAGS System Using Data/Instruction Grain Power Control. ISSCC 2007: 66-587 - [c48]Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada:
VLSI CAD Education and Exercise Course with Public Domain Tools. MSE 2007: 111-112 - 2006
- [j19]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. IEICE Trans. Electron. 89-C(3): 364-369 (2006) - [j18]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function. IEICE Trans. Electron. 89-C(3): 370-376 (2006) - [j17]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Noise Immunity Investigation of Low Power Design Schemes. IEICE Trans. Electron. 89-C(8): 1238-1247 (2006) - [j16]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Autonomous di/dt Control of Power Supply for Margin Aware Operation. IEICE Trans. Electron. 89-C(11): 1689-1694 (2006) - [j15]Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada:
A Structural Approach for Transistor Circuit Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3529-3537 (2006) - [j14]Taisuke Kazama, Makoto Ikeda, Kunihiro Asada:
LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3546-3550 (2006) - [c47]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
On-chip 8GHz non-periodic high-swing noise detector. DATE 2006: 670-671 - [c46]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE 2006: 884-889 - [c45]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. DDECS 2006: 147-148 - [c44]Makoto Ikeda, Hiroshi Yamauchi, Kunihiro Asada:
Tamper Resistivity Analysis for Nano-meter LSI with Process Variations. ICECS 2006: 387-390 - [c43]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. ICECS 2006: 704-707 - [c42]Yusuke Yachide, Makoto Ikeda, Kunihiro Asada:
High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine. ICECS 2006: 764-767 - [c41]Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada:
4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. ICECS 2006: 1007-1010 - [c40]Makoto Ikeda, Kin Hooi Dia, Kunihiro Asada:
Pre-conditioning Free Footless DCVSL for High-performance Datapaths. ICECS 2006: 1053-1056 - [c39]Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada:
Exact Minimum Logic Factoring via Quantified Boolean Satisfiability. ICECS 2006: 1065-1068 - [c38]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS 2006 - 2005
- [j13]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Trans. Electron. 88-C(1): 125-132 (2005) - [j12]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
On-chip di/dt Detector Circuit. IEICE Trans. Electron. 88-C(5): 782-787 (2005) - [j11]Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada:
A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells. IEICE Trans. Inf. Syst. 88-D(6): 1159-1167 (2005) - [j10]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1957-1963 (2005) - [j9]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Trans. Electron. 88-C(8): 1734-1739 (2005) - [j8]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3485-3491 (2005) - [j7]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique. IEEE J. Solid State Circuits 40(2): 444-453 (2005) - [c37]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Autonomous di/dt noise control scheme for margin aware operation. ESSCIRC 2005: 467-470 - [c36]Nan Li, Makoto Ikeda, Kunihiro Asada:
Analysis of low noise three-phase asynchronous data transmission. ESSCIRC 2005: 479-482 - [c35]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI 2005: 74-77 - [c34]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
On-chip non-periodic high-swing noise detector. ICECS 2005: 1-4 - [c33]Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada:
An algebraic approach for transistor circuit synthesis. ICECS 2005: 1-4 - [c32]Yusuke Yachide, Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Real-time 3-D measurement system based on light-section method using smart image sensor. ICIP (3) 2005: 1008-1111 - 2004
- [j6]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Smart Access Image Sensors for High-Speed and High-Resolution 3-D Measurement based on Light-Section Method. Intell. Autom. Soft Comput. 10(2): 105-128 (2004) - [j5]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding. IEEE J. Solid State Circuits 39(1): 246-251 (2004) - [j4]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution. IEEE J. Solid State Circuits 39(4): 622-628 (2004) - [j3]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture. IEEE J. Solid State Circuits 39(8): 1383-1387 (2004) - [c31]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154 - [c30]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
Design of real-time VGA 3-D image sensor using mixed-signal techniques. ASP-DAC 2004: 523-524 - [c29]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A word-parallel digital associative engine with wide search range based on Manhattan distance. CICC 2004: 295-298 - [c28]Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. DFT 2004: 87-95 - [c27]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380 - 2003
- [c26]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture. CICC 2003: 643-646 - [c25]Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Theoretical study of stubs for power line noise reduction [LSI applications]. CICC 2003: 715-718 - [c24]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A smart image sensor with high-speed feeble ID-beacon detection for augmented reality system. ESSCIRC 2003: 125-128 - [c23]Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design. ESSCIRC 2003: 189-192 - [c22]Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
High-speed position detector using new row-parallel architecture for fast collision prevention system. ISCAS (4) 2003: 788-791 - [c21]Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada:
Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42 - 2002
- [c20]Satoshi Sugiyama, Makoto Ikeda, Kunihiro Asada:
Quick power supply noise estimation using hierarchically derived transfer functions. ICECS 2002: 713-716 - [c19]Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
Logic synthesis for PLA with 2-input logic elements. ISCAS (3) 2002: 373-376 - [c18]Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. ASP-DAC/VLSI Design 2002: 166-171 - [c17]Tohru Ishihara, Kunihiro Asada:
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. ASP-DAC/VLSI Design 2002: 282-287 - 2001
- [c16]Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. ASP-DAC 2001: 3-4 - [c15]Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada:
A smart position sensor for 3-D measurement. ASP-DAC 2001: 21-22 - [c14]Jian Qiao, Makoto Ikeda, Kunihiro Asada:
Finding an optimal functional decomposition for LUT-based FPGA synthesis. ASP-DAC 2001: 225-230 - [c13]Tohru Ishihara, Kunihiro Asada:
A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC 2001: 456-461 - [c12]Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada:
Computational Cost Reduction in Extracting Inductance. ISQED 2001: 179-184 - 2000
- [j2]Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada:
A Binary Image Sensor for Motion Detection. J. Robotics Mechatronics 12(5): 508-514 (2000) - [c11]Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada:
A binary image sensor with flexible motion vector detection using block matching method. ASP-DAC 2000: 21-22 - [c10]Jian Qiao, Makoto Ikeda, Kunihiro Asada:
Optimum Functional Decomposition for LUT-Based FPGA Synthesis. FPL 2000: 555-564 - [c9]Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada:
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. ISQED 2000: 305-308
1990 – 1999
- 1999
- [c8]Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI 1999: 368-371 - [c7]Makoto Ikeda, Kunihiro Asada:
Standard design flows of Logic LSIs in Japanese universities and VDEC. MSE 1999: 8-9 - 1998
- [j1]Rimon Ikeno, Hiroshi Ito, Kunihiro Asada:
One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects. VLSI Design 6(1-4): 65-67 (1998) - [c6]Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC 1998: 323-324 - [c5]Tetsuhisa Mido, Kunihiro Asada:
An Analysis on VLSI Interconnection Considering Skin Effect. ASP-DAC 1998: 403-408 - 1997
- [c4]Tetsuhisa Mido, Kunihiro Asada:
Crosstalk noise in high density and high speed interconnections due to inductive coupling. ASP-DAC 1997: 215-220 - 1995
- [c3]Minkyu Song, Kunihiro Asada:
Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier. ISCAS 1995: 1568-1571 - 1994
- [c2]Makoto Ikeda, Kunihiro Asada:
A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. EDAC-ETC-EUROASIC 1994: 546-550 - 1992
- [c1]H. Zhang, Kunihiro Asada:
A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. Synthesis for Control Dominated Circuits 1992: 323-333
Coauthor Index
[j70] [c135] [j69] [j68] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [c134] [c133] [c132] [j60] [j59] [j57] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [j53] [c122] [c121] [c120] [c118] [c117] [c114] [j50] [c112] [c110] [c109] [j48] [c101] [j45] [c100] [c99] [c98] [c96] [c94] [j41] [j39] [j38] [c90] [c89] [j36] [j33] [j30] [j29] [j26] [c83] [c80] [c78] [c68] [c66] [c65] [j20] [c51] [c50] [c46] [c43] [c38] [j10] [j8] [c35] [c31] [c27]
[j65] [j48] [j47] [j46] [j45] [c100] [c94] [j44] [j42] [j40] [j37] [c92] [c88] [c87] [c86] [j35] [j33] [j32] [j30] [j29] [j26] [j25] [c84] [c83] [c81] [c79] [c77] [c75] [c73] [j24] [j23] [j22] [c70] [c67] [c66] [c65] [c64] [j21] [c63] [c62] [c61] [c60] [c59] [c57] [j20] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [j19] [j18] [j17] [j16] [j15] [j14] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [c37] [c36] [c35] [c34] [c33] [c32] [j6] [j5] [j4] [j3] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c16] [c15] [c14] [c12] [j2] [c11] [c10] [c9] [c8] [c7] [c6] [c2]
[j70] [j69] [j68] [j67] [j66] [j65] [j64] [j63] [j62] [c133] [c132] [j60] [j59] [j57] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [j56] [j55] [j54] [j53] [c122] [c121] [c120] [c119] [c117] [c116] [c115] [c114] [j52] [j51] [c112] [c111] [c110] [c109] [c107] [c106] [c105] [c102] [j46] [c98] [c96] [c95] [j43] [j40] [j38] [c90] [c89] [c85] [j33] [j32] [j30] [j29] [c83] [c81] [c79] [c72] [j24] [j23] [j22] [c70] [c68] [c66] [c65] [j21] [c62] [c61] [c60] [c59] [c57] [c56] [c49] [j19] [j16] [j13] [j12] [j9] [c37] [c25]
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