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ORCIDCICC 2003: San Jose, CA, USA
- Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003. IEEE 2003, ISBN 0-7803-7842-3
- Takashi Oshima
, Kenji Maio, Willy Hioe, Yoshiyuki Shibahara, Takeshi Doi:
Automatic tuning of RC filters and fast automatic gain control for CMOS low-IF transceiver. 5-8 - Artur J. Lewinski, José Silva-Martínez:
OTA linearity enhancement technique for high frequency applications with IM3 below -65dB. 9-12 - José Silva-Martínez, Joseph Adut, Miguel Rocha-Pérez:
A 58dB SNR 6th order broadband 10.7 MHz SC ladder filter. 13-16 - Kenneth W. H. Ng, Howard C. Luong:
A 28-MHz wide-band switched-capacitor bandpass filter with high attenuation. 17-20 - Yorgos Palaskas, Yannis P. Tsividis, Vito Boccuzzi:
A power efficient channel selection filter/coarse AGC with no range switching transients. 21-24 - Gilles-Eric Descamps, Satish Bagalkotkar:
The iFlow design factory infrastructure for a 17M-gate, 0.13μm, 333MHz design [SoC design]. 27-34 - Aurangzeb Khan, Kaushik Patel, Amit Aurora, Adnan Raza, Bidyut Parruck, Anandarup Bagchi, Abijit Ghosh, Boris Litinsky, Eric Hong, Eric Zhao, Jeremy Ngo, Kenson Ko, Leena Singh, Pavel Arnaudov, Peter Wu, Rama Ramakrishnan, Rami Zecharia, Shankar Channabasappa, Suril Kumar, Sanjay Wattal, Tony Wang, Uday Joshi, Zohar Golan, Zunning Luo, Duc-Ngoc Le, Irfan Ahmed, Frederick Chiu, King Y. Chow, Hiroyuki Furuzono, David Ge, Min Li, Martin Mueller, Son Nguyen, Trung Nguyen, Jean Saito, John Shen, Antonio Todesco, Allen Tsou, Demin Wang, Steven Yang, John Yu, Xia Zhong:
Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC. 35-38 - Dilip Krishnaswamy, Ray Stevens, Robert N. Hasbun, Juan R. Revilla, Chris Hagan:
The Intel® PXA800F wireless Internet-on-a-chip architecture and design. 39-42 - James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh:
SoC implementation issues for synthesizable embedded programmable logic cores. 45-48 - Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello:
Cyclone ™: a low-cost, high-performance FPGA. 49-52 - Kim Yaw Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit:
Regular logic fabrics for a via patterned gate array (VPGA). 53-56 - Tim Tuan, Bo-Cheng Lai:
Leakage power analysis of a 90nm FPGA. 57-60 - Andy Gean Ye, Jonathan Rose, David M. Lewis:
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. 61-64 - Chih-Kong Ken Yang, Koon-Lun Jackie Wong:
Analysis of timing recovery for multi-Gbps PAM transceivers. 67-72 - Rainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama:
A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator. 73-76 - Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran:
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. 77-80 - Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer:
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. 81-84 - Tzung-Yin Lee, Yuhua Cheng:
MOSFET HF distortion behavior and modeling for RF IC design. 87-90 - Ehsan Afshari, Ali Hajimiri:
Non-linear transmission lines for pulse shaping in silicon. 91-94 - Tak Shun Dickson Cheung, John R. Long, Kunal Vaed, Richard Volant, A. Chinthakindi, Chris M. Schnabel, J. Florkey, Z. X. He, Kenneth Stein:
Differentially-shielded monolithic inductors. 95-98 - Yutao Hu, Kartikeya Mayaram:
A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulation. 99-102 - Hyunchol Shin, Brett C. Walker, Dongling Pan, Jeremy Dunworth, James Jaffee:
Analysis of spectral spreading in a phase-modulated system for 1.75-GHz GSM RF transmitter design. 103-106 - Behnam Analui, Ali Hajimiri:
Statistical analysis of integrated passive delay lines. 107-110 - Bruce A. Wooley:
Cascaded noise-shaping modulators for oversampled data conversion. 113-114 - Yong-In Park, S. Karthikeyan, Wem Ming Koe, Zhongnong Jiang, Tiak-Chean Tan:
A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWA. 115-118 - Anas A. Hamoui, Kenneth W. Martin:
A 1.8-V 3-MS/s 13-bit ΔΣ A/D converter with pseudo data-weighted-averaging in 0.18-μm digital CMOS. 119-122 - Bharath Kumar Thandri, José Silva-Martínez, José Miguel Rocha-Pérez, Jing Wang:
A 92MHz, 80dB peak SNR SC bandpass ΣΔ modulator based on a high GBW OTA with no Miller capacitors in 0.35μm CMOS technology. 123-126 - Todd S. Kaplan, Jose M. Cruz-Albrecht, Mehran Mokttari, Dave Mattews, Joseph F. Jensen, M. Frank Chang:
A 1.3-GHz IF digitizer using a 4th-order continuous-time bandpass ΔΣ modulator. 127-130 - Susan Luschas, Richard Schreier, Hae-Seung Lee:
A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC. 131-134 - Takis Zourntos:
A 200-MHz continuous-time CMOS delta-sigma modulator featuring nonlinear feedback control. 135-138 - Robert Aigner:
High performance RF-filters suitable for above IC integration: film bulk-acoustic- resonators (FBAR) on silicon. 141-146 - Ping-Hsuan Hsieh, Jack Judy, Chih-Kong Ken Yang:
CMOS LC oscillator using variable mean frequency. 147-150 - Mamoru Ugajin, Tsuneo Tsukahara:
A 1-V 2.4-GHz FSK receiver with a complex BPF and a frequency doubler in CMOS/SOI. 151-154 - Mehmet R. Yuce, Wentai Liu, John Damiano, Bhaskar Bharath, Paul D. Franzon, Numan Sadi Dogan:
A low power PSK receiver for space applications in 0.35-μm SOI CMOS. 155-158 - Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner:
A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology. 159-162 - Takakuni Douseki, Tsuneo Tsukahara, Yoshifumi Yoshida, Fumiyasu Utsunomiya, Norio Hama:
A batteryless wireless system with MTCMOS/SOI circuit technology. 163-168 - Lawrence T. Clark:
Trends and challenges for wireless embedded DSPs. 171-176 - Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo:
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. 177-180 - Junichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. 181-184 - Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui:
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. 185-188 - Abhishek Bandyopadhyay, Paul E. Hasler:
A fully programmable CMOS block matrix transform imager architecture. 189-192 - Nam Sung Kim, Trevor N. Mudge, Richard B. Brown:
A 2.3Gb/s fully integrated and synthesizable AES Rijndael core. 193-196 - Chorng-Ping Chang:
MEMS for telecommunications: devices and reliability. 199-206 - Mei-Kei Ieong, Kathryn W. Guarini, Victor Chan, Kerry Bernstein, Rajiv V. Joshi, Jakub Kedzierski, Wilfred Haensch:
Three dimensional CMOS devices and integrated circuits. 207-213 - Arokia Nathan, Kapil Sakariya, Anil Kumar, Peyman Servati, Karim S. Karim, Denis Striakhilev, Andrei Sazonov:
Amorphous silicon TFT circuit integration for OLED displays on glass and plastic. 215-222 - Gary H. Bernstein:
Quantum-dot cellular automata by electric and magnetic field coupling. 223-229 - Gennady Gildenblat, Ten-Lon Chen, Xin Gu, Hailing Wang, Xiaowen Cai:
SP: an advanced surface-potential-based compact MOSFET model. 233-240 - Pin Su, Samel K. H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu:
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. 241-244 - Ke-Wei Su, Yi-Ming Sheu, Chung-Kai Lin, Sheng-Jier Yang, Wen-Jya Liang, Xuemei Xi, Chung-Shi Chiang, Jaw-Kang Her, Yu-Tai Chia, Carlos H. Diaz, Chenming Hu:
A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics. 245-248 - Bo Wan, Bo P. Hu, Lili Zhou, Chuanjin Richard Shi:
MCAST: an abstract-syntax-tree based model compiler for circuit simulation. 249-252 - Junjun Li, Sopan Joshi, Elyse Rosenbaum:
A Verilog-A compact model for ESD protection NMOSTs. 253-256 - James T. Doyle, Young-Jun Lee, Yong-Bin Kim:
An accurate DAC modeling technique based on wavelet theory. 257-260 - Syed Aon Mujtaba:
MIMO signal processing - the next frontier for capacity enhancement. 263-270 - David Garrett, Linda M. Davis, Stephan ten Brink, Bertrand M. Hochwald:
APP processing for high performance MIMO systems [receiver symbol detector]. 271-274 - Charles Thomas, Tom Prokop, Mark Bickerstaff, J. Niemasz, Pierre Bernadac, Patrice Saintot, R. Laufer, Dominique Bescher, R. Michel, Brett C. Walker, F. Derriennic, N. Burban, E. Le Pape, J. P. Moreau, I. Cha, S. Angioni, K. Mhirsi, J. Lee, P. Prat, G. Rogard, V. L'Aubin, D. Le Gall, C. Dagorn, D. Guillerm, P. Ragon, T. Goumis, M. Cooke, Benjamin Widdup, G. Zhou, David Garrett, C. Conan, P. Cabon, A. Carter, Chris Nicol, P. Keevill, P. Mankiewich:
An 8-user UMTS channel unit processor for 3GPP base station applications. 275-278 - Katsutoshi Seki, K. Mikami, A. Katayama, S. Suzuki, N. Shinohara, M. Nakabayashi:
Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems. 279-282 - J. M. Pierre Langlois, Dhamin Al-Khalili:
Low power direct digital frequency synthesizers in 0.18 μm CMOS. 283-286 - Yanlin Wu, Dengwei Fu, Alan N. Willson Jr.:
A 415 MHz direct digital quadrature modulator in 0.25-μm CMOS. 287-290 - Frank Herzel, Wolfgang Winkler, Johannes Borngräber:
An integrated 10 GHz quadrature LC-VCO in SiGe: C BiCMOS - technology for low-jitter applications. 293-296 - Sheng Ye, Lars C. Jansson, Ian Galton:
Techniques for in-band phase noise suppression in re-circulating DLLs. 297-300 - Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. 301-304 - Behzad Razavi:
A study of injection pulling and locking in oscillators. 305-312 - Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman:
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. 313-316 - Jongsun Kim, Zhiwei Xu, M. Frank Chang:
A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability. 317-320 - Lawrence Larson, Darryl Jessie:
Advances in RF packaging technologies for next-generation wireless communications applications [RFIC]. 323-330 - Marco Racanelli, Paul Kempf:
SiGe BiCMOS technology for communication products. 331-334 - Charlie Kuznia, Joe Ahadian, Mark Englekirk, Man Wong, Jean Richaud, Mike Pendleton, Dick Pommer, Ron Reedy:
Ultra-thin silicon-on-sapphire component technology for short reach parallel optical interconnects. 335-338 - Edward J. Nowak, Thomas Ludwig, Ingo Aller, Jakub Kedzierski, M. Leong, BethAnn Rainey, Matthew J. Breitwisch, V. Gemhoefer, Joachim Keinert, David M. Fried:
Scaling beyond the 65 nm node with FinFET-DGCMOS. 339-342 - Denny D. Tang, Carlos H. Diaz, Chih-Ping Chao, Humning Hsu, Chwan-Ying Lee, Chih-Sheng Chang, Yu-Tai Chia, Ming-Ta Yang, Jack Yuan-Chen Sun:
Foundry technology for 130nm and beyond SoC. 343-350 - Vassilios Gerousis:
Design and modeling challenges for 90 NM and 50 NM. 353-360 - Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez:
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. 361-364 - Sridhar Ramaswamy:
Analyzing the impact of supply and substrate noise on jitter in Gb/s serial links. 365-368 - Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto:
A substrate noise analysis methodology for large-scale mixed-signal ICs. 369-372 - Andreas Hermann, Markus Olbrich, Erich Barke:
Placing substrate contacts into mixed-signal circuits controlling circuit performance. 373-376 - David M. Colleran, Clemenz L. Portmann, Arash Hassibi, César A. R. Crusius, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee, Maria del Mar Hershenson:
Optimization of phase-locked loop circuits via geometric programming. 377-380 - Kostas Pagiamtzis, Ali Sheikholeslami:
Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories. 383-386 - Gen Kasai, Yukihiro Takarabe, Koji Furumi, Masato Yoneda:
200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme. 387-390 - Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. 391-394 - Yi-Chou Chen, C. T. Chen, J. Y. Yu, Chienying Lee, Chieh-Fang Chen, S. L. Lung, Rich Liu:
180nm Sn-doped Ge2Sb2Te5 chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applications. 395-398 - Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda:
Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. 399-402 - Shoichi Masui, Wataru Yokozeki, Michiya Oura, Tsuzumi Ninomiya, Kenji Mukaida, Yoshihisa Takayama, Toshiyuki Teramoto:
Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall. 403-406 - Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration. 409-412 - Jipeng Li, Un-Ku Moon:
A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique. 413-416 - Shinichi Hisano, Scott E. Sapp:
A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm. 417-420 - Mezyad M. Amourah, Haydar Bilhan, Feng Ying, Lieyi Fang, Gonggui Xu, Ramesh Chandrasekarad, Randall L. Geiger:
A 9b 165MS/s 1.8V pipelined ADC with all digital transistors amplifier. 421-424 - Patrick J. Quinn, Maxim Pribytko:
Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS. 425-428 - Gabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja:
A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer. 429-432 - Alireza Razzaghi, M.-C. Frank Chang:
A 10-b, 1-GSample/s track-and-hold amplifier using SiGe BiCMOS technology. 433-436 - Wendell B. Sander, Stephan V. Schell, Brian L. Sander:
Polar modulator for multi-mode cell phones. 439-445 - Sotoudeh Hamedi-Hagh, C. André T. Salama:
A 1 V, 8 GHz CMOS integrated phase shifted transmitter for wideband and varying envelope communication systems. 447-450 - Francesco Carrara, Antonino Scuden, Giuseppe Palmisano:
Wide-bandwidth fully integrated Cartesian feedback transmitter. 451-454 - Min Chen, Kevin H. Wang, Desong Zhao, Liang Dai, Zaw Soe, Paul Rogers:
A CMOS Bluetooth radio transceiver using a sliding-IF architecture. 455-458 - Enrico Sacchi, Ivan Bietti, Simone Erbat, Luns Tee, Paolo Vilmercati, Rinaldo Castello:
A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver. 459-462 - Ivan Bietti, Enrico Temporiti, Guido Albasini, Rinaldo Castello:
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques. 463-466 - Robert J. Drost, Robert David Hopkins, Ivan E. Sutherland:
Proximity communication. 469-472 - Young-Soo Sohn, Seung-Jun Bae, Hong-June Park, Changhyun Kim, Soo-In Cho:
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. 473-476 - James R. Talman, Steven L. Garverick, Geoffrey R. Lockwood:
Integrated circuit for high-frequency ultrasound annular array. 477-480 - Steven L. Garverick, Michael L. Nagy, Michael J. Kane, Jun Guo:
Bipolar pulse width modulation driver for MEMS electrostatic actuator arrays. 481-484 - Pablo M. Acosta-Serafini, Ichiro Masaki, Charles G. Sodini:
A 1/3" VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervals. 485-488 - Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez:
Piezoelectric power generation interface circuits. 489-492 - Mohammad R. Hoque, Ty McNutt, Jimmy Zhang, H. Alan Mantooth, Mohammad M. Mojarradi:
A high voltage Dickson charge pump in SOI CMOS. 493-496 - A. Campifelli, Carmen Bartic, Jean-Michel Friedt, K. De Keersmaecker, Wim Laureyn, Laurent A. Francis, F. Frederix, Gunter Reekmans, Angelina Angelova, Jan Suls, K. Bonroy, R. De Palma, Z. Cheng, Gustaaf Borghs:
Development of microelectronic based biosensors. 505-512 - Mark J. Milgrew, David R. S. Cumming, Paul A. Hammond:
The fabrication of scalable multi-sensor arrays using standard CMOS technology [chemical sensors]. 513-516 - Dean A. Scribner, Lee Johnson, Richard Klein, William E. Bassett, J. Grant Howard, Perry Skeath, Lucienne Wasserman, B. Wright, F. Keith Perkins, Martin Peckerar, B. J. Finch, Robert Graham, Walter C. Trautfield, S. Taylor, Mark S. Humayun:
A retinal prosthesis device based on an 80×40 hybrid microelectronic-microwire glass array. 517-520 - Michael W. Baker, Timothy Kuan-Ta Lu, Christopher D. Salthouse, Ji-Jon Sit, Serhii M. Zhak, Rahul Sarpeshkar:
A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends. 521-526 - Johan van der Tang, Ronald Dekker, Arthur H. M. van Roermund:
A surface-mounted RF IC technology demonstrated with a 10 GHz LC oscillator with copper coils. 529-532 - M. S. Lin, Ling Chen, J. Y. Lee, H. T. Liu, C. K. Chou, K. H. Wan, H. M. Chen, Kevin Chou, Roger Hsiao, Eric Lin:
A new IC interconnection scheme and design architecture for high performance ICs at very low fabrication cost - post passivation interconnection. 533-536 - Xiao Huo, Guo-Wei Xiao, Kevin J. Chen, Philip C. H. Chan:
Silicon-on-organic integration of a 2.4GHz VCO using high Q copper inductors and solder-bumped flip chip technology. 537-540 - Reza Navid, Thomas H. Lee, Robert W. Dutton:
Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit]. 543-546 - Albert C. Jerng, Charles G. Sodini:
The impact of device type and sizing on phase noise mechanisms [MOS VCOs]. 547-550 - Kachun Kwok, Howard C. Luong:
A 0.35-V 1.46-mW low-phase-noise oscillator with transformer feedback in standard 0.18-μm CMOS process. 551-554 - Axel D. Bemy, Ali M. Niknejad, Robert G. Meyer:
A wideband low-phase-noise CMOS VCO. 555-558 - Je-Kwang Cho, Han-Il Lee, Kyung-Suc Nah, Byeong-Ha Park:
A 2-GHz wide band low phase noise voltage-controlled oscillator with on-chip LC tank. 559-562 - Andrea Mazzanti, Paola Uggetti, Paolo Rossi, Francesco Svelto:
Injection locking LC dividers for low power quadrature generation. 563-566 - Dennis K. Ma, John R. Long, D. L. Hararne:
A subharmonically-injected quadrature LO generator for 17GHz WLAN applications. 567-570 - Robert Bogdan Staszewski, Dirk Leipold, John L. Wallberg, Paras T. Balsam:
Just-in-time gain estimation of an RF digitally-controlled oscillator. 571-574 - R. Wadhwa, A. Aggarwal, J. Edwards, M. Ehlert, J. Hoehn, G. Miao, Kadaba Lakshmikumar, John M. Khoury:
A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDES. 577-580 - Thomas W. Krawczyk Jr., Sam A. Steidl, Richard Alexander, James Pulver, Gary Kowalski, Craig Hornbuckle, David Rowe:
A 39.8Gb/s to 43.1Gb/s SFI-5 compliant 16: 1 multiplexer and 1: 16 demultiplexer for optical communication systems. 581-584 - Hamid Partovi, Bill Evans, Tom Wilson, Scott Shelton, Eric Naviasky, Ethiraj Sanjeevi, Yongli Wen, Karthik Gopalakrishnan, Sivaraman Chokalingam, Hugh Thompson, Mike Casas, Lingting Ye, Mike Hufford, Yujing Qiu, Michelle Williams, Jared James, Alberto Baldisserotto, Steven White, Steve Williams, Domenic Georgantas, Tom Gray:
A 62.5 Gb/s multi-standard SerDes IC. 585-588 - Vladimir Stojanovic, Mark Horowitz:
Modeling and analysis of high-speed links. 589-594 - G. Miao, P. Ju, D. Ng, John M. Khoury, Kadaba Lakshmikumar:
A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 μm CMOS. 595-598 - N. Tan, F. Caster, C. Eichrodt, S. O. George, B. Horng, J. Zhao:
A universal quad AFE with integrated filters for VDSL, ADSL, and G.SHDSL. 599-602 - Charles F. Hawkins, Ali Keshavarzi, Jaume Segura:
CMOS IC nanometer technology failure mechanisms. 605-611 - Jeanne Trinko Mechler, Raymond J. Bulaga, Jon Garlett:
In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self test. 613-616 - Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. 617-620 - Mohamed M. Hafed, Gordon W. Roberts:
A 5-channel, variable resolution, 10-GHz sampling rate coherent tester/oscilloscope IC and associated test vehicles. 621-624 - Terence Hook, Larry Wissel, David Mazgaj:
Estimation of Iddq for early chip and technology design decisions. 627-630 - Jody W. Gambles, Lowell H. Miles, J. Hass, W. Smith, Sterling R. Whitaker, Brant Smith:
An ultra-low-power, radiation-tolerant Reed Solomon encoder for space applications. 631-634 - Jin-Hyeok Choi, Takayasu Sakurai:
Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments. 635-638 - Benton H. Calhoun, Anantha P. Chandrakasan:
Standby voltage scaling for reduced power. 639-642 - Yusuke Oike, Makoto Ikeda, Kunihiro Asada:
A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture. 643-646 - Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Bums, Richard B. Brown:
Resonant clocking using distributed parasitic capacitance. 647-650 - Frank Pospiech, Stephen Olsen:
Embedded software in the SoC world. How HdS helps to face the HW and SW design challenge [hardware dependent software]. 653-658 - Ranianand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Uinh Ton, Sergey Shomurryev, Chong Lee, Shoujun Waiig, Huy Ngo, Malik Kdhani, Victor Maruri, Tin Lai, Tam Kpuyeu, Arch Zaliziiyak, Mei Luo, Toan Nguyen, Kazi Asaduzzaman, Siniardeep Maangat, John Lam, Rakesh Patel:
Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment. 659-662 - Cynthia Trigas:
Design challenges for system-in-package vs system-on-chip. 663-666 - Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A distributed crossbar switch scheduler for on-chip networks. 671-674 - Klaas-Jan de Langen, Johan H. Huijsing:
Low-voltage power-efficient operational amplifier design techniques - an overview. 677-684 - Masato Koutani, Yoshihisa Fujimoto, Masayuki Miyamoto:
A highly linear CMOS buffer circuit with an adjustable output impedance. 685-688 - Yonghui Tang, Randall L. Geiger:
High-frequency 750mV operational amplifier standard bulk CMOS process. 689-692 - Hoi Lee, Philip K. T. Mok:
Switching noise reduction techniques for switched-capacitor voltage doubler. 693-696 - G. de Cremoux, Y. Christoforou, I. van Loo:
A new method for multiplying the Miller capacitance using active components [voltage regulator example]. 697-700 - Brian N. Limketkai, Robert W. Brodersen:
An equation-based method for phase noise analysis [oscillator examples]. 703-706 - Jongsun Park, Khurram Muhammad, Kaushik Roy:
Efficient generation of 1/fα noise using a multi-rate filter bank. 707-710 - Jri Lee, Kenneth S. Kundert, Behzad Razavi:
Modeling of jitter in bang-bang clock and data recovery circuits. 711-714 - Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Theoretical study of stubs for power line noise reduction [LSI applications]. 715-718 - Mini Nanua, David T. Blaauw:
Noise analysis methodology for partially depleted SOI circuits. 719-722 - Hui Zheng, Byron Krauter, Lawrence T. Pileggi:
On-package decoupling optimization with package macromodels. 723-726
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