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2020 – today
- 2024
[c46]Daniel Yingling, Yimai Peng, Robert Vachon, Dipti Pal, Sagar Jariwala, Felipe G. Cabral, Jason Hu, Rajan Verma, Vamshidhar Chiranji, Anil Kumar, Santanu Sarma, Keith A. Bowman:
14.3 A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion. ISSCC 2024: 258-260- 2022
- [c45]Zhaoqing Wang
, Sung Justin Kim, Keith A. Bowman, Mingoo Seok:
Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators. CICC 2022: 1-8 - 2021
- [j21]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor. IEEE J. Solid State Circuits 56(3): 814-823 (2021) - [j20]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor. IEEE J. Solid State Circuits 56(4): 1166-1175 (2021) - [c44]Ping-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman:
Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE. ISSCC 2021: 402-403 - [c43]Arijit Raychowdhury, Mijung Noh, Keith A. Bowman:
Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee. ISSCC 2021: 488-489 - [c42]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Suresh Venkumahanti:
35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ Processor. ISSCC 2021: 494-496 - [c41]Nick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof:
F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. ISSCC 2021: 520-524 - [c40]Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham:
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC 2021: 539-540 - 2020
- [c39]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP. CICC 2020: 1-4 - [c38]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j19]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54(4): 1173-1184 (2019) - [c37]Francois Atallah, Keith A. Bowman, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury:
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. ISSCC 2019: 316-318 - [c36]Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury:
A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. VLSI Circuits 2019: 126- - 2018
- [j18]Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak:
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 53(1): 3-7 (2018) - [c35]Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman:
A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. VLSI Circuits 2018: 1-2 - [c34]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits 2018: 65-66 - 2017
- [c33]Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury:
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. CICC 2017: 1-4 - [c32]Makoto Takamiya, Yogesh K. Ramadass, Keith A. Bowman, Gerard Villar Pique, Shuichi Nagai, Dennis Sylvester:
F1: Integrated voltage regulators for SoC and emerging IoT systems. ISSCC 2017: 500-502 - 2016
- [j17]Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. IEEE J. Solid State Circuits 51(1): 8-17 (2016) - [j16]Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang:
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. J. Signal Process. Syst. 84(3): 295-307 (2016) - 2015
- [c31]Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine:
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. CICC 2015: 1-4 - [c30]Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. ISSCC 2015: 1-3 - 2014
- [c29]Alex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine:
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. CICC 2014: 1-4 - [c28]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - [c27]Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine:
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. ITC 2014: 1 - [c26]Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang:
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. SiPS 2014: 192-197 - 2013
- [j15]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De:
Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test 30(6): 8-17 (2013) - [j14]Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz:
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits 48(4): 907-916 (2013) - [c25]Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz:
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED 2013: 181-186 - [c24]Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi:
Welcome to ISQED 2013. ISQED 2013 - 2012
- [c23]Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman:
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC 2012: 7-16 - [c22]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c21]Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz:
A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC 2012: 94-95 - [e1]Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni:
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. IEEE 2012, ISBN 978-1-4673-1034-5 [contents] - 2011
- [j13]Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 208-217 (2011) - [j12]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46(1): 184-193 (2011) - [j11]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De:
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46(1): 194-208 (2011) - [j10]Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De:
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits 46(4): 797-805 (2011) - [j9]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De:
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2017-2025 (2011) - 2010
- [c20]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c19]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De:
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 - [c18]Keith A. Bowman, James W. Tschanz:
Resilient microprocessor design for improving performance and energy efficiency. ICCAD 2010: 85-88 - [c17]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 - [c16]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175 - [c15]James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 - [c14]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah:
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [j8]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 44(1): 49-63 (2009) - [j7]Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson:
Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1679-1690 (2009) - [c13]Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 - [c12]James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik:
Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD 2009: 71-73 - 2008
- [c11]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC 2008: 402-403 - 2007
- [c10]Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 - [c9]Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson:
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. ISLPED 2007: 50-55 - 2006
- [j6]Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin:
Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26(6): 30-39 (2006) - [c8]Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De:
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 - [c7]Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar:
Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5 - 2005
- [c6]James W. Tschanz, Keith A. Bowman, Vivek De:
Variation-tolerant circuits: circuit solutions and techniques. DAC 2005: 762-763 - [c5]Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge:
Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD 2005: 535-540 - [c4]Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De:
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED 2005: 26-29 - 2002
- [j5]Keith A. Bowman, Steven G. Duvall, James D. Meindl:
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits 37(2): 183-190 (2002) - 2001
- [j4]Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. 9(6): 899-912 (2001) - [c3]Keith A. Bowman, James D. Meindl:
Impact of within-die parameter fluctuations on future maximum clock frequency distributions. CICC 2001: 229-232 - 2000
- [j3]Keith A. Bowman, Xinghai Tang, John C. Eble, James D. Menldl:
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. IEEE J. Solid State Circuits 35(8): 1186-1193 (2000) - [j2]Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl:
A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 235-251 (2000) - [c2]Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED 2000: 167-172 - [c1]Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl:
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP 2000: 147-148
1990 – 1999
- 1999
- [j1]Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl:
A physical alpha-power law MOSFET model. IEEE J. Solid State Circuits 34(10): 1410-1414 (1999)
Coauthor Index
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