research-article

Scan chain clustering for test power reduction

Authors:

Hans-Joachim Wunderlich,

Michael E. Imhof,

Christian G. Zoellin,

Nicolas MaedingAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 828 - 833

https://doi.org/10.1145/1391469.1391680

Published: 08 June 2008 Publication History

Abstract

An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern.

In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. It is not dependent on a test set and can improve the performance of any test power reduction technique consequently. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration.

The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits.

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Cited By

Lee SCho KChoi SKang S(2020)A New Logic Topology-Based Scan Chain Stitching for Test-Power ReductionIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.300437167:12(3432-3436)Online publication date: Dec-2020
https://doi.org/10.1109/TCSII.2020.3004371
Dutta AKundu SChattopadhyay SDas B(2015)A hardware based low temperature solution for VLSI testing using decompressor side masking2015 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2015.7168714(637-640)Online publication date: May-2015
https://doi.org/10.1109/ISCAS.2015.7168714
Chen MOrailoglu A(2014)Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay TestIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225681022:4(734-746)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2256810
Show More Cited By

Index Terms

Scan chain clustering for test power reduction
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The EDA Consortium
IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

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Published: 08 June 2008

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DAC '08

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Lee SCho KChoi SKang S(2020)A New Logic Topology-Based Scan Chain Stitching for Test-Power ReductionIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2020.300437167:12(3432-3436)Online publication date: Dec-2020
https://doi.org/10.1109/TCSII.2020.3004371
Dutta AKundu SChattopadhyay SDas B(2015)A hardware based low temperature solution for VLSI testing using decompressor side masking2015 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2015.7168714(637-640)Online publication date: May-2015
https://doi.org/10.1109/ISCAS.2015.7168714
Chen MOrailoglu A(2014)Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay TestIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225681022:4(734-746)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2256810
Lee DHan T(2014)An improvement technique for the test compression ratio and application time of multiple expansion scan chain based SoC using new cost function2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2014.6908369(129-132)Online publication date: Aug-2014
https://doi.org/10.1109/MWSCAS.2014.6908369
Li MCui AYu T(2014)An improved scan cell ordering method using the scan cells with complementary outputs2014 International Symposium on Integrated Circuits (ISIC)10.1109/ISICIR.2014.7029573(103-106)Online publication date: Dec-2014
https://doi.org/10.1109/ISICIR.2014.7029573
Kahng AKang INath SHenkel J(2013)Incremental multiple-scan chain ordering for ECO flip-flop insertionProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561965(705-712)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561965
Kahng AKang INath S(2013)Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2013.6691192(705-712)Online publication date: Nov-2013
https://doi.org/10.1109/ICCAD.2013.6691192
Lee L(2013)Observation-Oriented ATPG and Scan Chain Disabling for Capture Power ReductionJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5404-x29:5(625-634)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1007/s10836-013-5404-x
Wang WKuang JLiu PPeng XYou Z(2012)Switching activity reduction for scan-based BIST using weighted scan input dataIEICE Electronics Express10.1587/elex.9.8749:10(874-880)Online publication date: 2012
https://doi.org/10.1587/elex.9.874
Chen MOrailoglu A(2012)Scan power reduction for linear test compression schemes through seed selectionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217350920:12(2170-2183)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2173509
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