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- research-articleJune 2018
Protecting the supply chain for automotives and IoTs
DAC '18: Proceedings of the 55th Annual Design Automation ConferenceArticle No.: 89, Pages 1–4https://doi.org/10.1145/3195970.3199851Modern automotive systems and IoT devices are designed through a highly complex, globalized, and potentially untrustworthy supply chain. Each player in this supply chain may (1) introduce sensitive information and data (collectively termed "assets") ...
- ArticleAugust 2015
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy
DSD '15: Proceedings of the 2015 Euromicro Conference on Digital System DesignPages 280–283https://doi.org/10.1109/DSD.2015.95In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic ...
- ArticleMay 2015
Clock Domain Imbalances and Their Impact on Test Architecture
NATW '15: Proceedings of the 2015 IEEE 24rd North Atlantic Test WorkshopPages 7–10https://doi.org/10.1109/NATW.2015.10Clock architecture in digital designs goes throughan iterative cycle of timing analysis, routing and placement andfixes to meet timing. At a higher level, each of these steps must bedone in different scenarios for example: test mode and functionalmode. ...
- research-articleNovember 2013
Scalable and efficient analog parametric fault identification
Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be ...
- ArticleMay 2011
A Testable Realization for Decimal Multipliers
ISMVL '11: Proceedings of the 2011 41st IEEE International Symposium on Multiple-Valued LogicPages 248–253https://doi.org/10.1109/ISMVL.2011.45We propose a testable decimal multiplication circuit under the single cell fault model. The multiplier consists of iterative logic arrays of partial product generators and adders. We also give a set of test patterns to detect single faults in the ...
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- ArticleMay 2011
Improved DFT for Testing Power Switches
ETS '11: Proceedings of the 2011 Sixteenth IEEE European Test SymposiumPages 7–12https://doi.org/10.1109/ETS.2011.63Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a ...
- articleMay 2010
Complex oscillation-based test and its application to analog filters
IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCSPI), Volume 57, Issue 5Pages 956–969https://doi.org/10.1109/TCSI.2010.2046956Testing is a critical factor for modern large-scale mixed-mode circuits. Strategies for mitigating test cost and duration include moving significant parts of the test hardware on-chip. This paper presents a novel low-overhead approach for design for ...
- research-articleMay 2009
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSIPages 517–522https://doi.org/10.1145/1531542.1531659In this paper, we propose a novel way to save test power, using the DFT based technique as basic method and post-generation filling as complementary. In this architecture, two methods of clustering flip-flops into scan chains are presented. One is ...
- research-articleJune 2008
Scan chain clustering for test power reduction
- Melanie Elm,
- Hans-Joachim Wunderlich,
- Michael E. Imhof,
- Christian G. Zoellin,
- Jens Leenstra,
- Nicolas Maeding
DAC '08: Proceedings of the 45th annual Design Automation ConferencePages 828–833https://doi.org/10.1145/1391469.1391680An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be ...
- articleAugust 2007
The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach
Journal of Electronic Testing: Theory and Applications (JELT), Volume 23, Issue 4Pages 293–307https://doi.org/10.1007/s10836-006-0711-0Test and inspection are an increasingly costly element of electronic system design and manufacture and so it is critical that the cost effectiveness of test and inspection are well understood. This paper presents techniques which may be used to assess ...
- ArticleJuly 2006
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors
DAC '06: Proceedings of the 43rd annual Design Automation ConferencePages 1083–1088https://doi.org/10.1145/1146909.1147183For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. aliasing). In this paper, we first propose a mathematical framework to ...
- articleApril 2006
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips
IEICE - Transactions on Information and Systems (TROIS), Volume E89-D, Issue 4Pages 1490–1497https://doi.org/10.1093/ietisy/e89-d.4.1490With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead ...
- ArticleJuly 2005
Extending boundary-scan to perform a memory built-in self-test
ICC'05: Proceedings of the 9th International Conference on CircuitsArticle No.: 23, Pages 1–5We present a novel test architecture which combines IEEE 1149.1 Boundary-Scan with a Memory Built-In Self-Test. The TDI pin is used for serially shifting in the test data into a test data register which is connected to the memory. The finite state ...
- ArticleNovember 2004
Testing for Missing-Gate Faults in Reversible Circuits
ATS '04: Proceedings of the 13th Asian Test SymposiumPages 100–105https://doi.org/10.1109/ATS.2004.84Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the ...
- articleAugust 2004
Oscillation Test Strategy: A Case Study
Journal of Electronic Testing: Theory and Applications (JELT), Volume 20, Issue 4Pages 389–396https://doi.org/10.1023/B:JETT.0000039606.61081.52In this paper is proposed as a case study the test of a folded cascode operational amplifier using the Oscillation Test Strategy (OTS). This Operational Amplifier (OPA) is chosen in order to evaluate the ability of OTS to test a more complex amplifier ...
- articleAugust 2004
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications (JELT), Volume 20, Issue 4Pages 357–373https://doi.org/10.1023/B:JETT.0000039604.64927.0fThis paper proposes a comprehensive model for test planning and design space exploration in a core-based environment. The proposed approach relies on the reuse of available system resources for the definition of the test access mechanism, and for the ...
- articleFebruary 2003
Multiple Scan Chain Design for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications (JELT), Volume 19, Issue 1Pages 37–48https://doi.org/10.1023/A:1021991828423Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be ...
- ArticleApril 2002
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus
This work presents a design for test method for continuous time active filters of any order, using the IEEE 1149.4 as its backbone structure. The method relies on the synthesis of filter transfer functions using partial fraction extraction. Transfer ...
- articleOctober 2001
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters
Journal of Electronic Testing: Theory and Applications (JELT), Volume 17, Issue 5Pages 373–383https://doi.org/10.1023/A:1012747017838Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The ...
- research-articleJuly 1998
Pentium Pro Processor Design for Test and Debug
This article describes the Design for Test (DFT) and silicon debug features of the Pentium Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing ...