ASIC Challenges: Emerging from a Primordial Soup
In his keynote speech given at the International Verilog-VHDL Conference (March 1998), Wilf Corrigan, the chair and CEO of LSI Logic, described some of the challenges facing the ASIC industry today and in the future. Corrigan, one of Silicon Valley's ...
Analyzing Packaging Trade-Offs During System Design
The primary drivers behind today's high-density electronic systems are time-to-market and cost. The very existence of many commercial products depends on finding quick design solutions that meet increasingly challenging performance and cost ...
Modeling and Optimizing the Costs of Electronic Systems
In recent years, multi-chip modules (MCMs) and other high density packages (HDPs) have become more and more important for high performance electronics. They offer interesting new possibilities to overcome the size, weight, and power constraints for ...
VLSI, MCM, and WSI: A Design Comparison
This article provides a quantitative comparison of VLSI, MCM and WSI on the basis of silicon area, substrate size and power consumption. These parameters are estimated and then calculated for two example processors: a stand-alone computer and a ...
The Role of the Good-Die Project in Miniaturized-System Design
The implementation of complex electronic systems using High Density Packaging (HDP) technologies requires an IC-like "first-time right" design approach, as rework and prototyping for such technologies can be extremely expensive. On the other hand, most ...
Testing NASA's 3D-Stack MCM Space Flight Computer
Advanced packaging technologies such as 3D chip stacking, multichip modules (MCMs), and 3D stacks of MCMs provide opportunities for significant reductions in system mass, volume and power. They also pose major testing challenges that need to be resolved ...
Guest Editor's Introduction: Microprocessor Testing Today
First Page of the Article
Design of Cache Test Hardware on the HP PA8500
The PA7300 was the first PA-RISC microprocessor to incorporate an on-chip cache. To test its 128-Kbyte memory, test hardware was included consisting of an input register, an output MISR, an LFSR address source, and a state machine. The state machine was ...
Testability Features of the AMD-K6 Microprocessor
This article describes the testability features and test pattern development methodologies for the AMD-K6 Microprocessor. The embedded Design for Testability (DFT) structures and test strategy provide high quality manufacturing tests.
Test Development for Second-Generation ColdFire Microprocessors
A case study of the development of the design for test methodology of the second generation of the ColdFire(r) Microprocessor family is described from the viewpoint of goals, initial strategy, and implementation. Methodology includes at-speed scan path ...
Pentium Pro Processor Design for Test and Debug
This article describes the Design for Test (DFT) and silicon debug features of the Pentium Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing ...
Testing the 500-MHz IBM S/390 Microprocessor
- Thomas G. Foote,
- Dale E. Hoffman,
- William V. Huott,
- Timothy J. Koprowski,
- Mary P. Kusko,
- Bryan J. Robbins
This article describes the design-for-test framework of the 500MHz CMOS central processor (CP) used in the IBM Generation-5 S/390 ??line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe ...
Test Strategy for the PowerPC 750 Microprocessor
Time to market demands for the PowerPC 750 microprocessor require new test strategy approaches to improving the product test quality, reliability, and debug process. The total time to market includes not just the design cycle time to the initial tapeout,...
Alpha 21164 Manufacturing Test Development and Coverage Analysis
Today's competitive market demands high quality levels for electronic devices including state-of-the-art microprocessors. Unfortunately, the full-custom design methodology and performance constraints of the Alpha 21164, a deep sub-micron, superscalar ...
Effective Built-In Self-Test for Booth Multipliers
Module generators provided by library vendors supply chip designers with optimized Booth multipliers which are widely used, as embedded cores, in both general purpose datapath structures and specialized Digital Signal Processors. Testing of such ...
Rapid Hardware Prototyping on RPM-2
Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurability by software at low cost. Entire systems can be built in which some parts are programmable. Such systems implement various architectures. Each ...
A D&T Roundtable: Challenges for Low-Power and High-Performance Chips
Microprocessor and other lC performance continues to improve at historic rates, with no visible end in sight for the next 10 years. However, we are starting to encounter a power wall. This is true for high-performance components as well as for low-power ...