research-article

Pentium Pro Processor Design for Test and Debug

Authors:

Adrian Carbine,

Derek FelthamAuthors Info & Claims

IEEE Design & Test, Volume 15, Issue 3

Pages 77 - 82

https://doi.org/10.1109/54.706037

Published: 01 July 1998 Publication History

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Abstract

This article describes the Design for Test (DFT) and silicon debug features of the Pentium Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models. Results show that this approach was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.

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Chen YChen TLi LWu RLiu DHu W(2013)Deterministic Replay Using Global ClockACM Transactions on Architecture and Code Optimization10.1145/2445572.244557310:1(1-28)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1145/2445572.2445573
Gort MDe Paula FKuan JAamodt THu AWilton SYang J(2012)Formal-analysis-based trace computation for post-silicon debugIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216641620:11(1997-2010)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2166416
Wang HGao XChen YTang DHu WCheung PWawrzynek J(2010)A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723160(283-283)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723160
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Pentium Pro Processor Design for Test and Debug
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Information

Published In

IEEE Design & Test Volume 15, Issue 3

July 1998

124 pages

ISSN:0740-7475

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 1998

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Cited By

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Chen YChen TLi LWu RLiu DHu W(2013)Deterministic Replay Using Global ClockACM Transactions on Architecture and Code Optimization10.1145/2445572.244557310:1(1-28)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1145/2445572.2445573
Gort MDe Paula FKuan JAamodt THu AWilton SYang J(2012)Formal-analysis-based trace computation for post-silicon debugIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216641620:11(1997-2010)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2166416
Wang HGao XChen YTang DHu WCheung PWawrzynek J(2010)A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1723112.1723160(283-283)Online publication date: 21-Feb-2010
https://dl.acm.org/doi/10.1145/1723112.1723160
Das S(2007)Fault tolerant systems design in VLSI using data compression under constraints of failure probabilitiesProceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics10.5555/1984502.1984559(329-337)Online publication date: 14-Dec-2007
https://dl.acm.org/doi/10.5555/1984502.1984559
Sarangi STiwari ATorrellas J(2006)PhoenixProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2006.41(26-37)Online publication date: 9-Dec-2006
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