IEEE Design & Test

This issue of IEEE Design & Test of Computers is focused on the theme of digitally enhanced wireless systems. Guest Editors Haralampos Stratigopoulos and Alberto Valdes-Garcia have worked diligently to put together this special issue with a set of four ...

This special issue of IEEE Design & Test of Computers provides an overview of the challenges, current practice, and future research directions of digitally enhanced wireless systems. The author provides an overview of the technical articles and features ...

In this review article, the author revisits the digitization journey of wireless systems and the motivations that have driven this research field, gives a brief yet concise summary of state-of-the-art solutions, and offers insights for future ...

This article discusses the trade-offs involved in the implementation of a highly digital receiver and then describes a direct-sampling architecture which provides a wide range of runtime adaptability by varying parameters such as sample rate, filter ...

This article discusses the goals and recent achievements of the HEALICs program. The program's aim is to enhance wireless systems with sensors, actuators, and mixed-signal control loops in order to improve their performance yield.

This article discusses a self-healing 60-GHz transceiver architecture which employs information collected from on-chip sensors to intelligently adjust various tuning knobs and significantly improve the post-healing performance yield.

Presents an interview conducted with Lip-Bu Tan, President and CEO of Cadence Design Systems.

Booting and debugging the functionality of silicon samples are known to be challenging and time-consuming tasks, even more so in cost-constrained environments. The authors describe their creative solutions used to bring up Stanford Smart Memories (SSM), ...

Intermittent faults, being serious concerns for deep-submicron integrated circuits, are not well studied in the literature. This paper performs fault injection simulation to analyze the impact of intermittent faults, which is an important step towards ...

Analog circuits designed in submicrometer nodes suffer from process variations, typically requiring calibration in order to center their performance parameters and to recover yield loss. This article presents a design flow to find appropriate tuning ...

This paper presents the details of a standard, named OpenDFM, which describes an efficient method to ensure manufacturability of integrated circuits that are designed at advanced technology nodes of today and one that can scale to address similar issues ...

This paper focuses on the V4-2007 extension of the Standard Test Data Format (STDF). STDF has been used as the standard representation for logging test data from automatic test equipment (ATE). This format however lacked a key capability, i.e., storing ...

A year ago, this column contemplated the road ahead for semiconductor-based products that build on basic design, test, process, and device technologies. In late 2011, a workshop on the "Future of IT and Society" presented several broad visions of how ...

Every active design and programmer needs an understanding of what is coming in the computing domain and when, and how to be prepared for it. Vajda's book is more than a textbook summary of what is, it also contains a strong author's viewpoint about what ...