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ORCIDJianlei Yang 0001
Person information
- affiliation: Beihang University, School of Computer Science and Engineering, Beijing, China
- affiliation (PhD 2014): Tsinghua University, Beijing, China
Other persons with the same name
- Jianlei Yang — disambiguation page
- Jianlei Yang 0002 — Beihang University, School of Electronic and Information Engineering, Beijing, China
- Jianlei Yang 0003 — Hebei University, Baoding, China
- Jianlei Yang 0004 — State Key Laboratory of Satellite Navigation System and Equipment Technology, Shijiazhuang, China
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2020 – today
- 2024
[j28]Yingjie Qi
, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu:
Architectural Implications of GNN Aggregation Programming Abstractions. IEEE Comput. Archit. Lett. 23(1): 125-128 (2024)- [j27]Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu:
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. IEEE Trans. Computers 73(12): 2693-2707 (2024) - [j26]Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao:
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 906-918 (2024) - [j25]Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao:
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. IEEE Trans. Neural Networks Learn. Syst. 35(9): 12913-12923 (2024) - [c44]Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu:
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. DAC 2024: 187:1-187:6 - [c43]Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao:
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. DAC 2024: 209:1-209:6 - [c42]Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu:
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. DAC 2024: 229:1-229:6 - [c41]Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu:
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. DAC 2024: 239:1-239:6 - [c40]Yicheng Huang, Xueyan Wang, Tianao Dai, Jianlei Yang, Zhaojun Lu, Xiaotao Jia, Gang Qu, Weisheng Zhao:
LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators. ITC-Asia 2024: 1-6 - [i29]Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu:
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. CoRR abs/2404.05605 (2024) - [i28]Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao:
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. CoRR abs/2404.09497 (2024) - [i27]Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu:
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. CoRR abs/2404.09544 (2024) - [i26]Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu:
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. CoRR abs/2408.12840 (2024) - 2023
- [j24]Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Sci. China Inf. Sci. 66(4) (2023) - [j23]Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao:
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4695-4705 (2023) - [c39]Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu:
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. DAC 2023: 1-6 - [c38]Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang:
Lossy and Lossless (L2) Post-training Model Size Compression. ICCV 2023: 17500-17510 - [i25]Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu:
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. CoRR abs/2303.10875 (2023) - [i24]Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang:
Lossy and Lossless (L2) Post-training Model Size Compression. CoRR abs/2308.04269 (2023) - [i23]Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu:
Architectural Implications of GNN Aggregation Programming Abstractions. CoRR abs/2310.12184 (2023) - [i22]Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao:
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory. CoRR abs/2310.20424 (2023) - [i21]Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao:
TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices. CoRR abs/2311.01759 (2023) - 2022
- [j22]Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao:
S2 Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. IEEE Trans. Computers 71(6): 1440-1452 (2022) - [j21]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao:
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. IEEE Trans. Computers 71(10): 2462-2472 (2022) - [j20]Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao:
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5333-5342 (2022) - [j19]Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang:
Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2694-2706 (2022) - [c37]Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao:
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. DAC 2022: 331-336 - [c36]Han Wan, Hongzhen Luo, Zihao Zhong, Jianlei Yang:
Exploring the Factors of Students' Online Learning Based On Structural Equation Modeling. TALE 2022: 423-429 - [i20]Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao:
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. CoRR abs/2203.15439 (2022) - [i19]Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. CoRR abs/2204.09989 (2022) - [i18]Jianlei Yang, Xiaopeng Gao, Weisheng Zhao:
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. CoRR abs/2207.12229 (2022) - 2021
- [j18]Xiaoyi Wang, Shaobin Ma, Sheldon X.-D. Tan, Chase Cook, Liang Chen, Jianlei Yang, Wenjian Yu:
Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 507-520 (2021) - [j17]Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao:
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Trans. Neural Networks Learn. Syst. 32(4): 1703-1712 (2021) - [c35]Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao:
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. CIKM 2021: 3283-3287 - [c34]Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu:
Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. RTAS 2021: 445-448 - [i17]Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu:
Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. CoRR abs/2104.03058 (2021) - [i16]Xin Guo, Jianlei Yang, Haoyi Zhou, Xucheng Ye, Jianxin Li:
RoSearch: Search for Robust Student Architectures When Distilling Pre-trained Language Models. CoRR abs/2106.03613 (2021) - [i15]Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao:
S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. CoRR abs/2106.07894 (2021) - [i14]Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao:
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. CoRR abs/2108.09081 (2021) - [i13]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao:
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. CoRR abs/2112.00471 (2021) - 2020
- [j16]Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao:
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. CCF Trans. High Perform. Comput. 2(3): 272-281 (2020) - [j15]Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao:
Prototyping federated learning on edge computing systems. Frontiers Comput. Sci. 14(6): 146318 (2020) - [j14]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao:
Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. ACM J. Emerg. Technol. Comput. Syst. 16(4): 37:1-37:18 (2020) - [j13]Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao:
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 789-802 (2020) - [j12]Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao:
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 803-815 (2020) - [j11]Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang:
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 108-120 (2020) - [c33]Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao:
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. DAC 2020: 1-6 - [c32]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao:
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. DAC 2020: 1-6 - [c31]Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen:
Accelerating CNN Training by Pruning Activation Gradients. ECCV (25) 2020: 322-338 - [c30]Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang:
Dual-Plane Switch Architecture for Time-Triggered Ethernet. ACM Great Lakes Symposium on VLSI 2020: 375-379 - [c29]Jianlei Yang, Xiaopeng Gao, Weisheng Zhao:
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. ACM Great Lakes Symposium on VLSI 2020: 567-572 - [c28]Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao:
Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. ISCAS 2020: 1-4 - [c27]Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang:
TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations. KDD 2020: 824-832 - [i12]Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao:
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. CoRR abs/2005.03857 (2020) - [i11]Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang:
TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework with Anonymized Intermediate Representations. CoRR abs/2005.11480 (2020) - [i10]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao:
Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques. CoRR abs/2006.01425 (2020) - [i9]Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao:
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. CoRR abs/2007.10702 (2020) - [i8]Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao:
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. CoRR abs/2007.13595 (2020)
2010 – 2019
- 2019
- [j10]Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang:
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Sustain. Comput. Informatics Syst. 22: 206-218 (2019) - [j9]Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao:
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 57-69 (2019) - [c26]Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao:
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. DAC 2019: 193 - [c25]Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao:
Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. ISCAS 2019: 1-5 - [c24]Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao:
SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. ISCAS 2019: 1-5 - [c23]Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao:
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. ISVLSI 2019: 203-206 - [i7]Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao:
SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing. CoRR abs/1902.06886 (2019) - [i6]Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao:
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. CoRR abs/1906.05096 (2019) - [i5]Xucheng Ye, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao:
Accelerating CNN Training by Sparsifying Activation Gradients. CoRR abs/1908.00173 (2019) - [i4]Zirui Xu, Zhao Yang, Jinjun Xiong, Jianlei Yang, Xiang Chen:
ELFISH: Resource-Aware Federated Learning on Heterogeneous Edge Devices. CoRR abs/1912.01684 (2019) - 2018
- [j8]Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng:
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. J. Comput. Sci. Technol. 33(5): 966-983 (2018) - [c22]Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao:
Spintronics based stochastic computing for efficient Bayesian inference system. ASP-DAC 2018: 580-585 - [c21]Xufeng Li, Jianlei Yang, Richong Zhang, Hongyuan Ma:
A Novel Approach on Entity Linking for Encyclopedia Infoboxes. CCKS 2018: 103-115 - [c20]Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao:
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. FPT 2018: 346-349 - [i3]Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao:
Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation. CoRR abs/1802.02789 (2018) - [i2]Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao:
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. CoRR abs/1810.12137 (2018) - 2017
- [c19]Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao:
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. ICCAD 2017: 474-481 - [c18]Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang:
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD 2017: 305-312 - [c17]Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi:
Generative adversarial network based scalable on-chip noise sensor placement. SoCC 2017: 239-242 - [c16]Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang:
Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. TrustCom/BigDataSE/ICESS 2017: 844-852 - [i1]Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Li, Weisheng Zhao:
Spintronics based Stochastic Computing for Efficient Bayesian Inference System. CoRR abs/1711.01125 (2017) - 2016
- [j7]Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li:
Spintronic Memristor as Interface Between DNA and Solid State Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 212-221 (2016) - [j6]Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li:
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 380-393 (2016) - [j5]Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao:
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. 65(4): 1755-1768 (2016) - [j4]Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao:
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3310-3322 (2016) - [c15]Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu:
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI 2016: 133-136 - [c14]Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie:
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD 2016: 118 - [c13]Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li:
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. ISVLSI 2016: 110-115 - [c12]You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao:
A novel circuit design of true random number generator using magnetic tunnel junction. NANOARCH 2016: 123-128 - 2015
- [j3]Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2617-2628 (2015) - [c11]Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai:
Early stage real-time SoC power estimation using RTL instrumentation. ASP-DAC 2015: 779-784 - [c10]Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia:
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. ACM Great Lakes Symposium on VLSI 2015: 69-74 - [c9]Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li:
An overview on memristor crossabr based neuromorphic circuit and architecture. VLSI-SoC 2015: 52-56 - 2014
- [j2]Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 899-912 (2014) - [j1]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2103-2116 (2014) - [c8]Wei Zhao, Yici Cai, Jianlei Yang:
Fast vectorless power grid verification using maximum voltage drop location estimation. ASP-DAC 2014: 861-866 - [c7]Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou:
Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT 2014: 161-166 - 2013
- [c6]Wei Zhao, Yici Cai, Jianlei Yang:
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. ASP-DAC 2013: 163-168 - [c5]Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao:
Selected inversion for vectorless power grid verification by exploiting locality. ICCD 2013: 257-263 - 2012
- [c4]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush : Efficient transient simulation for power grid analysis. ICCAD 2012: 653-659 - 2011
- [c3]Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze:
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI 2011: 199-204 - [c2]Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: A linear simulator for power grid. ICCAD 2011: 482-487 - [c1]Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Fast poisson solver preconditioned method for robust power grid analysis. ICCAD 2011: 531-536
Coauthor Index
[j27] [j26] [j25] [c44] [c43] [c41] [c40] [i29] [i28] [i27] [i26] [j24] [j23] [c39] [i25] [i22] [i21] [j22] [j21] [j20] [c37] [i20] [i19] [i18] [j17] [c35] [c34] [i17] [i15] [i14] [i13] [j16] [j15] [j14] [j13] [j12] [j11] [c33] [c32] [c29] [c28] [i12] [i10] [i9] [i8] [j9] [c26] [c25] [c24] [c23] [i7] [i6] [i5] [j8] [c22] [c20] [i3] [i2] [c19] [i1] [j6] [j5] [j4] [c12] [c10]
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-23 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
