research-article

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization

Authors:

C. N. SzeAuthors Info & Claims

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Pages 199 - 204

https://doi.org/10.1145/1973009.1973049

Published: 02 May 2011 Publication History

Abstract

Buered clock tree synthesis (CTS) is increasingly critical as VLSI technology continually scales down. Many researches have been done on this topic due to its key role in CTS, but current approaches either lack the obstacle-avoiding functionality or lead to large clock latency and/or skew. This paper presents a new obstacle-avoiding CTS approach with separate clock tree construction and buer insertion stages based on an integral view to explore the global optimization space. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buer positions, and a fast heuristic buer insertion algorithm. Experimental results show the eectiveness of our CTS approach with significantly improved skew and latency than [6] by 46% and 63% on average, and 15.3% reduction in skew than [5]. Our OBB heuristic obtains 36% improvement in skew than the classic balanced bipartition algorithm (BB) in [10].

References

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X.-W Shih, Y.-W. Chang, Fast timing-model independent bufferedclock-tree synthesis, In Proc. DAC, pp. 80--85, 2010

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J. L. Tsai, T.-H. Chen, and C. C.-P. Chen, Zero skew clock treeoptimization with buffer insertion/sizing and wire sizing, In IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.23, pages. 565--572, 2004.

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Shiyan Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, Weiping Shi,and C. N. Sze, Fast algorithms for slew constrained minimum cost-buffering, In IEEE Trans. Computer-Aided Design, vol.26, pp.2009--2022, 2007.

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W. Shi and Z. Li, A fast algorithm for opitmal buffer insertion, In IEEE Trans. Computer-Aided Design, vol. 24, no. 6, pp. 879--891, 2005.

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Z. Li and W. Shi, An O(bn2) time algorithm for buffer insertionwith b buffer types, In Proc. DATE, pp. 1324--1329, 2005.

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Cited By

Chentouf MEl Abidine Alaoui Ismaili Z(2022)A PUS based nets weighting mechanism for power, hold, and setup timing optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2022.01.00684:C(122-130)Online publication date: 1-May-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.01.006
Arumugam SViswanaathan L(2016)A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architectureInternational Journal of Circuit Theory and Applications10.1002/cta.227745:4(550-570)Online publication date: 24-Oct-2016
https://doi.org/10.1002/cta.2277
Saha PSaha SSamanta T(2015)Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles2015 28th International Conference on VLSI Design10.1109/VLSID.2015.81(447-451)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.81
Show More Cited By

Index Terms

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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cover image ACM Conferences

GLSVLSI '11: Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

May 2011

496 pages

ISBN:9781450306676

DOI:10.1145/1973009

General Chairs:
David Atienza
EPFL, Switzerland
,
Yuan Xie
Penn State University, USA
,
Program Chairs:
Jose L. Ayala
Federal University of Pernambuco, Brazil
,
Ken Stevens
University of Utah, USA

Copyright © 2011 ACM.

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Published: 02 May 2011

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GLSVLSI '11: Great Lakes Symposium on VLSI 2011

May 2 - 4, 2011

Lausanne, Switzerland

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Chentouf MEl Abidine Alaoui Ismaili Z(2022)A PUS based nets weighting mechanism for power, hold, and setup timing optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2022.01.00684:C(122-130)Online publication date: 1-May-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.01.006
Arumugam SViswanaathan L(2016)A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architectureInternational Journal of Circuit Theory and Applications10.1002/cta.227745:4(550-570)Online publication date: 24-Oct-2016
https://doi.org/10.1002/cta.2277
Saha PSaha SSamanta T(2015)Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles2015 28th International Conference on VLSI Design10.1109/VLSID.2015.81(447-451)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.81
Yici Cai Chao Deng Qiang Zhou Hailong Yao Feifei Niu Sze C(2015)Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer InsertionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.230017423:1(142-155)Online publication date: Jan-2015
https://doi.org/10.1109/TVLSI.2014.2300174
Deng CCai YZhou Q(2015)Fast synthesis of low power clock trees based on register clusteringSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085444(303-309)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085444
Deng CCai YZhou QChen Z(2015)An efficient buffer sizing algorithm for clock trees considering process variations2015 6th Asia Symposium on Quality Electronic Design (ASQED)10.1109/ACQED.2015.7274017(108-113)Online publication date: Aug-2015
https://doi.org/10.1109/ACQED.2015.7274017
Deng CCai YZhou Q(2015)Register Clustering Methodology for Low Power Clock Tree SynthesisJournal of Computer Science and Technology10.1007/s11390-015-1531-430:2(391-403)Online publication date: 13-Mar-2015
https://doi.org/10.1007/s11390-015-1531-4
Deng CCai YZhou Q(2014)A register clustering algorithm for low power clock tree synthesis2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865147(389-392)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865147
Rakai LFarshidi ABehjat LWestwick DKoh CSze C(2013)Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizesProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451956(154-161)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451956

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