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A fast algorithm for optimal buffer insertion

Published: 01 November 2006 Publication History

Abstract

The classic buffer insertion algorithm of van Ginneken has time and space complexity O(n2), where n is the number of possible buffer positions. For more than a decade, van Ginneken's algorithm has been the foundation of buffer insertion. In this paper, we present a new algorithm that computes the same optimal buffer insertion, but runs much faster. For 2-pin nets, our time complexity is O(nlogn) and space complexity is O(n). For multipin nets, our time complexity is O(nlog2n) and space complexity is O(nlogn). The speedup is achieved by four novel techniques: predictive pruning, candidate tree, fast redundancy check, and fast merging. On industrial test cases, the new algorithms is 2-80 times faster than van Ginneken's algorithm and uses 1/4-1/500 of the memory. Since van Ginneken's algorithm and its variations are used by most existing algorithms on buffer insertion and buffer sizing, our new algorithm significantly improves the performance of all these algorithms. The predictive pruning technique has been applied to buffer cost minimization (Shi et al., 2004), and significantly improved the running time.

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  • (2018)COSATProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196016(1-6)Online publication date: 24-Jun-2018
  • (2018)Interconnect Optimization Considering Multiple Critical PathsProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178237(132-138)Online publication date: 25-Mar-2018
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Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 24, Issue 6
November 2006
171 pages

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IEEE Press

Publication History

Published: 01 November 2006

Author Tags

  1. Buffer insertion
  2. Elmore delay
  3. data structure
  4. interconnect
  5. routing

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Cited By

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  • (2021)A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAsProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447047(135-142)Online publication date: 22-Mar-2021
  • (2018)COSATProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196016(1-6)Online publication date: 24-Jun-2018
  • (2018)Interconnect Optimization Considering Multiple Critical PathsProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178237(132-138)Online publication date: 25-Mar-2018
  • (2015)GasStationProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840939(861-866)Online publication date: 2-Nov-2015
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  • (2011)Algorithmic tuning of clock trees and derived non-tree structuresProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132396(279-282)Online publication date: 7-Nov-2011
  • (2011)Shedding physical synthesis area bloatVLSI Design10.1155/2011/5030252011(1-10)Online publication date: 1-Jan-2011
  • (2011)Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimizationProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973049(199-204)Online publication date: 2-May-2011
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  • (2010)ContangoProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871279(1468-1473)Online publication date: 8-Mar-2010
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