Cited By
View all- Gore GTang XGaillardon PLienig JBehjat LYang S(2021)A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAsProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447047(135-142)Online publication date: 22-Mar-2021
- Lu CJiang I(2018)COSATProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196016(1-6)Online publication date: 24-Jun-2018
- Hu JZhou YWei YQuay SReddy LTellez GNam GChu CBustany I(2018)Interconnect Optimization Considering Multiple Critical PathsProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178237(132-138)Online publication date: 25-Mar-2018
- Show More Cited By