Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
  • Suriano L, Lima D and de la Torre E. Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. Applied Reconfigurable Computing. Architectures, Tools, and Applications. (136-150).

    https://doi.org/10.1007/978-3-030-44534-8_11

  • Qadri M, Qadri N and McDonald-Maier K. (2016). Fuzzy logic based energy and throughput aware design space exploration for MPSoCs. Microprocessors & Microsystems. 40:C. (113-123). Online publication date: 1-Feb-2016.

    https://doi.org/10.1016/j.micpro.2015.08.001

  • Zhang D, Li S, Liu Y, Hu X, He X, Zhang Y, Zhang P and Yang H. (2016). A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications. ACM Transactions on Design Automation of Electronic Systems. 21:2. (1-32). Online publication date: 28-Jan-2016.

    https://doi.org/10.1145/2797135

  • Cilardo A and Fusella E. (2016). Design automation for application-specific on-chip interconnects. Integration, the VLSI Journal. 52:C. (102-121). Online publication date: 1-Jan-2016.

    https://doi.org/10.1016/j.vlsi.2015.07.017

  • Zhongqi Li , Qouneh A, Joshi M, Wangyuan Zhang , Xin Fu and Tao Li . (2015). Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1. (170-183). Online publication date: 1-Jan-2015.

    https://doi.org/10.1109/TVLSI.2014.2300477

  • Huang K, Haid W, Bacivarov I, Keller M and Thiele L. (2012). Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications. ACM Transactions on Embedded Computing Systems. 11:1. (1-23). Online publication date: 1-Mar-2012.

    https://doi.org/10.1145/2146417.2146425

  • Chen Y, Chiou L and Chang H. A fast and effective dynamic trace-based method for analyzing architectural performance. Proceedings of the 16th Asia and South Pacific Design Automation Conference. (591-596).

    /doi/10.5555/1950815.1950933

  • Plyaskin R and Herkersdorf A. A method for accurate high-level performance evaluation of MPSoC architectures using fine-grained generated traces. Proceedings of the 23rd international conference on Architecture of Computing Systems. (199-210).

    https://doi.org/10.1007/978-3-642-11950-7_18

  • Lee C, Kim S and Ha S. (2010). A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification. Journal of Signal Processing Systems. 58:2. (193-213). Online publication date: 1-Feb-2010.

    https://doi.org/10.1007/s11265-009-0351-6

  • Lee G, Chen Y, Mattavelli M and Jang E. (2009). Algorithm/architecture co-exploration of visual computing on emergent platforms. IEEE Transactions on Circuits and Systems for Video Technology. 19:11. (1576-1587). Online publication date: 1-Nov-2009.

    https://doi.org/10.1109/TCSVT.2009.2031376

  • Chiou L, Chen Y and Lee C. (2009). System-level bus-based communication architecture exploration using a pseudoparallel algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:8. (1213-1223). Online publication date: 1-Aug-2009.

    https://doi.org/10.1109/TCAD.2009.2021733

  • Schirner G and Dömer R. (2009). Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ACM Transactions on Embedded Computing Systems. 8:1. (1-29). Online publication date: 1-Dec-2008.

    https://doi.org/10.1145/1457246.1457250

  • Raman B and Chakraborty S. (2008). Application-specific workload shaping in multimedia-enabled personal mobile devices. ACM Transactions on Embedded Computing Systems. 7:2. (1-22). Online publication date: 1-Feb-2008.

    https://doi.org/10.1145/1331331.1331334

  • Madl G, Dutt N and Abdelwahed S. Performance estimation of distributed real-time embedded systems by discrete event simulations. Proceedings of the 7th ACM & IEEE international conference on Embedded software. (183-192).

    https://doi.org/10.1145/1289927.1289958

  • Loghi M, Benini L and Poncino M. (2007). Power macromodeling of MPSoC message passing primitives. ACM Transactions on Embedded Computing Systems. 6:4. (31-es). Online publication date: 1-Sep-2007.

    https://doi.org/10.1145/1274858.1274869

  • Sedcole P, Cheung P, Constantinides G and Luk W. (2007). Run-time integration of reconfigurable video processing systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:9. (1003-1016). Online publication date: 1-Sep-2007.

    https://doi.org/10.1109/TVLSI.2007.902203

  • Cho Y, Zergainoh N, Yoo S, Jerraya A and Choi K. (2007). Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. Design Automation for Embedded Systems. 11:2-3. (167-191). Online publication date: 1-Sep-2007.

    https://doi.org/10.1007/s10617-007-9004-9

  • Oh T, Yi Y and Ha S. Communication architecture simulation on the virtual synchronization framework. Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation. (3-12).

    /doi/10.5555/1776200.1776205

  • Huang K and Thiele L. Performance analysis of multimedia applications using correlated streams. Proceedings of the conference on Design, automation and test in Europe. (912-917).

    /doi/10.5555/1266366.1266563

  • Erbas C, Pimentel A, Thompson M and Polstra S. (2007). A framework for system-level modeling and simulation of embedded systems architectures. EURASIP Journal on Embedded Systems. 2007:1. (2-2). Online publication date: 1-Jan-2007.

    https://doi.org/10.1155/2007/82123

  • Zhu X, Qin W and Malik S. (2006). Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:7. (707-716). Online publication date: 1-Jul-2006.

    https://doi.org/10.1109/TVLSI.2006.878266

  • Kim S and Ha S. (2006). Efficient exploration of bus-based system-on-chip architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:7. (681-692). Online publication date: 1-Jul-2006.

    https://doi.org/10.1109/TVLSI.2006.878260

  • Lahiri K, Raghunathan A and Lakshminarayana G. (2006). The Lotterybus on-chip communication architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:6. (596-608). Online publication date: 1-Jun-2006.

    https://doi.org/10.1109/TVLSI.2006.878210

  • Kachris C and Vassiliadis S. Analysis of a reconfigurable network processor. Proceedings of the 20th international conference on Parallel and distributed processing. (187-187).

    /doi/10.5555/1898953.1899127

  • Pasricha S and Dutt N. COSMECA. Proceedings of the conference on Design, automation and test in Europe: Proceedings. (700-705).

    /doi/10.5555/1131481.1131680

  • Dumitrascu F, Bacivarov I, Pieralisi L, Bonaciu M and Jerraya A. Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. Proceedings of the conference on Design, automation and test in Europe: Designers' forum. (166-171).

    /doi/10.5555/1131355.1131390

  • Coussy P, Casseau E, Bomel P, Baganne A and Martin E. (2006). A formal method for hardware IP design and integration under I/O and timing constraints. ACM Transactions on Embedded Computing Systems. 5:1. (29-53). Online publication date: 1-Feb-2006.

    https://doi.org/10.1145/1132357.1132359

  • Pimentel A, Erbas C and Polstra S. (2006). A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels. IEEE Transactions on Computers. 55:2. (99-112). Online publication date: 1-Feb-2006.

    https://doi.org/10.1109/TC.2006.16

  • Pimentel A. A case for visualization-integrated system-level design space exploration. Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation. (455-464).

    https://doi.org/10.1007/11512622_48

  • Blume H, von Sydow T, Becker D and Noll T. Modeling noc architectures by means of deterministic and stochastic petri nets. Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation. (374-383).

    https://doi.org/10.1007/11512622_40

  • Kim S, Im C and Ha S. (2005). Schedule-aware performance estimation of communication architecture for efficient design space exploration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:5. (539-552). Online publication date: 1-May-2005.

    https://doi.org/10.1109/TVLSI.2004.842912

  • Cho Y, Yoo S, Choi K, Zergainoh N and Jerraya A. Scheduler implementation in MP SoC design. Proceedings of the 2005 Asia and South Pacific Design Automation Conference. (151-156).

    https://doi.org/10.1145/1120725.1120793

  • Kalla P, Hu X and Henkel J. A flexible framework for communication evaluation in SoC design. Proceedings of the 2005 Asia and South Pacific Design Automation Conference. (956-959).

    https://doi.org/10.1145/1120725.1120766

  • Murali S, Benini L and De Micheli G. Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. Proceedings of the 2005 Asia and South Pacific Design Automation Conference. (27-32).

    https://doi.org/10.1145/1120725.1120737

  • Gries M. (2004). Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal. 38:2. (131-183). Online publication date: 1-Dec-2004.

    https://doi.org/10.1016/j.vlsi.2004.06.001

  • Kim S, Im C and Ha S. Efficient exploration of on-chip bus architectures and memory allocation. Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. (248-253).

    https://doi.org/10.1145/1016720.1016779

  • Maxiaguine A, Zhu Y, Chakraborty S and Wong W. Tuning SoC platforms for multimedia processing. Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. (128-133).

    https://doi.org/10.1145/1016720.1016753

  • Deb A, Jantsch A and Öberg J. System design for DSP applications in transaction level modeling paradigm. Proceedings of the 41st annual Design Automation Conference. (466-471).

    https://doi.org/10.1145/996566.996698

  • Thepayasuwan N and Doboli A. Hardware-Software Co-Design of Resource Constrained Systems on a Chip. Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7. (818-823).

    /doi/10.5555/977399.977952

  • Coppola M, Curaba S, Grammatikakis M, Maruccia G and Papariello F. OCCN. Proceedings of the conference on Design, automation and test in Europe - Volume 3.

    /doi/10.5555/968880.969273

  • Ueda K, Sakanushi K, Takeuchi Y and Imai M. Architecture-Level Performance Estimation for IP-Based Embedded Systems. Proceedings of the conference on Design, automation and test in Europe - Volume 2.

    /doi/10.5555/968879.969144

  • Loghi M, Angiolini F, Bertozzi D, Benini L and Zafalon R. Analyzing On-Chip Communication in a MPSoC Environment. Proceedings of the conference on Design, automation and test in Europe - Volume 2.

    /doi/10.5555/968879.969124

  • Deb A, Jantsch A and Öberg J. System Design for DSP Applications Using the MASIC Methodology. Proceedings of the conference on Design, automation and test in Europe - Volume 1.

    /doi/10.5555/968878.969085

  • Shin C, Kim Y, Chung E, Choi K, Kong J and Eo S. Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. Proceedings of the conference on Design, automation and test in Europe - Volume 1.

    /doi/10.5555/968878.968965

  • Coppola M, Curaba S, Grammatikakis M, Locatelli R, Maruccia G and Papariello F. (2004). OCCN. Journal of Systems Architecture: the EUROMICRO Journal. 50:2-3. (129-163). Online publication date: 1-Feb-2004.

    https://doi.org/10.1016/j.sysarc.2003.07.002

  • Maxiaguine A, Künzli S, Chakraborty S and Thiele L. Rate analysis for streaming applications with on-chip buffer constraints. Proceedings of the 2004 Asia and South Pacific Design Automation Conference. (131-136).

    /doi/10.5555/1015090.1015122

  • Chakraborty S, Künzli S, Thiele L, Herkersdorf A and Sagmeister P. (2003). Performance evaluation of network processor architectures. Computer Networks: The International Journal of Computer and Telecommunications Networking. 41:5. (641-665). Online publication date: 5-Apr-2003.

    https://doi.org/10.1016/S1389-1286(02)00454-1

  • Deb A, Oberg J and Jantsch A. Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology. Proceedings of the conference on Design, Automation and Test in Europe - Volume 1.

    /doi/10.5555/789083.1022872

  • Gries M, Kulkarni C, Sauer C and Keutzer K. Comparing Analytical Modeling with Simulation for Network Processors. Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2.

    /doi/10.5555/1022685.1022959

  • Cho Y, Lee G, Yoo S, Choi K and Zergainoh N. Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2.

    /doi/10.5555/1022685.1022939

  • Kim J and Kim T. Trace-driven rapid pipeline architecture evaluation scheme for ASIP design. Proceedings of the 2003 Asia and South Pacific Design Automation Conference. (129-134).

    https://doi.org/10.1145/1119772.1119798

  • Wild T, Foag J, Pazos N and Brunnbauer W. Mapping and Scheduling for Architecture Exploration of Networking SoCs. Proceedings of the 16th International Conference on VLSI Design.

    /doi/10.5555/832285.835537

  • Lahiri K, Dey S and Raghunathan A. (2002). Communication-Based Power Management. IEEE Design & Test. 19:4. (118-130). Online publication date: 1-Jul-2002.

    https://doi.org/10.1109/MDT.2002.1018140

  • Lahiri K, Dey S and Raghunathan A. Communication architecture based power management for battery efficient system design. Proceedings of the 39th annual Design Automation Conference. (691-696).

    https://doi.org/10.1145/513918.514094

  • Lahiri K, Raghunathan A and Dey S. Fast system-level power profiling for battery-efficient system design. Proceedings of the tenth international symposium on Hardware/software codesign. (157-162).

    https://doi.org/10.1145/774789.774822