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- research-articleApril 2024
Algebraic and Boolean Methods for SFQ Superconducting Circuits
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 588–593https://doi.org/10.1109/ASP-DAC58780.2024.10473899Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing ...
- research-articleApril 2024
In Medio Stat Virtus*: Combining Boolean and Pattern Matching
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 404–410https://doi.org/10.1109/ASP-DAC58780.2024.10473889Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. This process is performed by means of local replacements that are extracted by matching sections of the subject graph to ...
- research-articleApril 2024
Towards Multiphase Clocking in Single-Flux Quantum Systems
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 582–587https://doi.org/10.1109/ASP-DAC58780.2024.10473879Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive electronics technologies. SFQ systems operate at tens of gigahertz with up to three orders of magnitude smaller power as compared to CMOS. In conventional SFQ systems, most ...
- research-articleDecember 2023
Fanout-Bounded Logic Synthesis for Emerging Technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 5Pages 1415–1428https://doi.org/10.1109/TCAD.2023.3339440In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. Moreover, some such technologies, e.g., adiabatic quantum-flux-parametron (AQFP), pose ...
- short-paperJune 2023
Compound Logic Gates for Pipeline Depth Minimization in Single Flux Quantum Integrated Systems
GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023Pages 421–425https://doi.org/10.1145/3583781.3590287Superconductive electronics is a promising candidate for supplementing or replacing existing CMOS VLSI systems. Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive technologies operating at tens of gigahertz while reducing the ...
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- research-articleMarch 2023
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 11Pages 3958–3971https://doi.org/10.1109/TCAD.2023.3256341Logic resynthesis is one of the core problems in modern peephole logic optimization algorithms. Given a target function and a set of existing functions, logic resynthesis asks for a circuit reusing some of the existing functions and generating the target. ...
- research-articleMarch 2023
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 42, Issue 3Pages 914–927https://doi.org/10.1109/TCAD.2022.3184633Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors [referred to as reconfigurable field-effect transistors (RFETs)] enable dynamic reconfiguration to ...
- research-articleMarch 2023
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions
Integration, the VLSI Journal (INTG), Volume 89, Issue CPages 248–260https://doi.org/10.1016/j.vlsi.2022.12.008AbstractLogic Synthesis From Partial Specifications (LSFPS) is the problem of finding the hardware implementation of a Boolean function from a partial knowledge of its care set. The elements missing from the specifications are ...
Highlights- Logic synthesis is a particular case of synthesis from partial specifications.
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- research-articleJanuary 2023
Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation ConferencePages 152–158https://doi.org/10.1145/3566097.3567895The Adiabatic Quantum-Flux Parametron (AQFP) is an energy-efficient superconducting logic family. AQFP technology requires buffer and splitting elements (B/S) to be inserted to satisfy path-balancing and fanout-branching constraints. B/S insertion ...
- research-articleAugust 2022
A Simulation-Guided Paradigm for Logic Synthesis and Verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 41, Issue 8Pages 2573–2586https://doi.org/10.1109/TCAD.2021.3108704This article proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high quality, expressive simulation patterns are pregenerated to be reused in multiple runs of optimization and verification algorithms, ...
- research-articleAugust 2022
Beyond local optimality of buffer and splitter insertion for AQFP circuits
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferencePages 445–450https://doi.org/10.1145/3489517.3530661Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Buffer and splitter (B/S) cells must be inserted to an AQFP circuit to meet the technology-imposed constraints on path balancing and fanout branching. These cells ...
- invited-talkApril 2022
Design and Optimization of Quantum Electronic Circuits
ISPD '22: Proceedings of the 2022 International Symposium on Physical DesignPage 139https://doi.org/10.1145/3505170.3512294Quantum electronic circuits where the logic information is processed and stored in single flux quanta promise efficient computation in a performance/power metric, and thus are of utmost interest as possible replacement or enhancement of CMOS. Several ...
- research-articleMay 2022
Majority-based design flow for AQFP superconducting family
- Giulia Meuli,
- Vinicius Possani,
- Rajinder Singh,
- Siang-Yun Lee,
- Alessandro Tempia Calvino,
- Dewmini Sudara Marakkalage,
- Patrick Vuillod,
- Luca Amaru,
- Scott Chase,
- Jamil Kawa,
- Giovanni De Micheli
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 34–39Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring superconducting ...
- research-articleMay 2022
tweedledum: a compiler companion for quantum computing
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 7–12This work presents tweedledum---an extensible open-source library aiming at narrowing the gap between high-level algorithms and physical devices by enhancing the expressive power of existing frameworks. For example, it allows designers to insert ...
- research-articleJanuary 2022
A Versatile Mapping Approach for Technology Mapping and Graph Optimization
ASPDAC '22: Proceedings of the 27th Asia and South Pacific Design Automation ConferencePages 410–416https://doi.org/10.1109/ASP-DAC52403.2022.9712552This paper proposes a versatile mapping approach that has three objectives: i) it can map from one technology-independent graph representation to another; ii) it can map to a cell library; iii) it supports logic rewriting. The method is cut-based, ...
- research-articleJanuary 2022
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis
ASPDAC '22: Proceedings of the 27th Asia and South Pacific Design Automation ConferencePages 395–402https://doi.org/10.1109/ASP-DAC52403.2022.9712526The paper presents a novel DAG-aware Boolean rewriting algorithm for restructuring combinational logic before technology mapping. The algorithm, called window rewriting, repeatedly selects small parts of the logic and replaces them with more compact ...
- research-articleJanuary 2022
Efficient Preparation of Cyclic Quantum States
ASPDAC '22: Proceedings of the 27th Asia and South Pacific Design Automation ConferencePages 460–465https://doi.org/10.1109/ASP-DAC52403.2022.9712522Universal quantum algorithms that prepare arbitrary n-qubit quantum states require O(2n) gate complexity. The complexity can be reduced by considering specific families of quantum states depending on the task at hand. In particular, multipartite quantum ...
- research-articleDecember 2021
LUT-Based Optimization For ASIC Design Flow
- Luca Amarú,
- Vinicius Possani,
- Eleonora Testa,
- Felipe Marranghello,
- Christopher Casares,
- Jiong Luo,
- Patrick Vuillod,
- Alan Mishchenko,
- Giovanni De Micheli
2021 58th ACM/IEEE Design Automation Conference (DAC)Pages 871–876https://doi.org/10.1109/DAC18074.2021.9586132Look-up Table (LUT) mapping and optimization is an important step in Field Programmable Gate Arrays (FPGAs) design. The effectiveness of LUT synthesis improved dramatically in the last decades, thanks to optimization and mapping innovations naturally ...
- research-articleJanuary 2021
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits
ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation ConferencePages 779–785https://doi.org/10.1145/3394885.3431606Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-...