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  • Anwer J, Meisner S and Platzner M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime 2013 International Conference on ReConFigurable Computing and FPGAs (ReConFig). 10.1109/ReConFig.2013.6732280. 978-1-4799-2079-2. (1-6).

    http://ieeexplore.ieee.org/document/6732280/

  • Liu S, Pittman R, Forin A and Gaudiot J. (2013). Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems. ACM Transactions on Embedded Computing Systems. 12:3. (1-21). Online publication date: 10-Mar-2013.

    https://doi.org/10.1145/2442116.2442122

  • Cardoso J, F. Coutinho J and Diniz P. (2013). Related Work. Compilation and Synthesis for Embedded Reconfigurable Systems. 10.1007/978-1-4614-4894-5_7. (181-195).

    https://link.springer.com/10.1007/978-1-4614-4894-5_7

  • Jara-Berrocal A and Gordon-Ross A. An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips. Proceedings of the ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors. (219-222).

    https://doi.org/10.1109/ASAP.2011.6043272

  • Sironi F and Cuoccio A. Self-aware adaptation via implementation hot-swap for heterogeneous computing. Proceedings of the 2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments. (1-8).

    https://doi.org/10.1109/CHANGE.2011.6172449

  • Osborne W, Luk W, Coutinho J and Mencer O. Energy reduction by systematic run-time reconfigurable hardware deactivation. Transactions on High-Performance Embedded Architectures and Compilers IV. (354-369).

    /doi/10.5555/2172445.2172467

  • Jevtic R and Carreras C. Power Measurement Methodology for FPGA Devices. IEEE Transactions on Instrumentation and Measurement. 10.1109/TIM.2010.2047664. 60:1. (237-247).

    http://ieeexplore.ieee.org/document/5475274/

  • Osborne W, Luk W, Coutinho J and Mencer O. (2011). Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation. Transactions on High-Performance Embedded Architectures and Compilers IV. 10.1007/978-3-642-24568-8_18. (354-369).

    http://link.springer.com/10.1007/978-3-642-24568-8_18

  • Sironi F, Triverio M, Hoffmann H, Maggio M and Santambrogio M. Self-Aware Adaptation in FPGA-based Systems. Proceedings of the 2010 International Conference on Field Programmable Logic and Applications. (187-192).

    https://doi.org/10.1109/FPL.2010.43

  • Paulsson K, Hübner M and Becker J. (2009). Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems. Microprocessors & Microsystems. 33:1. (46-52). Online publication date: 1-Feb-2009.

    https://doi.org/10.1016/j.micpro.2008.08.006

  • Noguera J, Esser R, Paulsson K, Hübner M and Becker J. (2009). Towards Novel Approaches in Design Automation for FPGA Power Optimization. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. 10.1007/978-3-540-95948-9_42. (419-428).

    http://link.springer.com/10.1007/978-3-540-95948-9_42

  • Paulsson K, Hubner M and Becker J. (2008). Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization 2008 International Conference on Field Programmable Logic and Applications (FPL). 10.1109/FPL.2008.4630044. 978-1-4244-1960-9. (699-700).

    http://ieeexplore.ieee.org/document/4630044/

  • Osborne W, Luk W, Coutinho J and Mencer O. (2008). Reconfigurable design with clock gating 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). 10.1109/ICSAMOS.2008.4664863. 978-1-4244-1985-2. (187-194).

    http://ieeexplore.ieee.org/document/4664863/

  • Glas B, Klimm A, Sander O, Müller-Glaser K and Becker J. A system architecture for reconfigurable trusted platforms. Proceedings of the conference on Design, automation and test in Europe. (541-544).

    https://doi.org/10.1145/1403375.1403505

  • Paulsson K, Hübner M and Becker J. Cost-and power optimized FPGA based system integration. Proceedings of the conference on Design, automation and test in Europe. (50-55).

    https://doi.org/10.1145/1403375.1403390

  • Glas B, Klimm A, Sander O, Muller-Glaser K and Becker J. (2008). A System Architecture for Reconfigurable Trusted Platforms 2008 Design, Automation and Test in Europe. 10.1109/DATE.2008.4484907. 978-3-9810801-3-1. (541-544).

    http://ieeexplore.ieee.org/document/4484907/

  • Paulsson K, Hubner M and Becker J. (2008). Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs 2008 Design, Automation and Test in Europe. 10.1109/DATE.2008.4484659. 978-3-9810801-3-1. (50-55).

    http://ieeexplore.ieee.org/document/4484659/

  • Paulsson K, Hubner M, Becker J, Philippe J and Gamrat C. (2007). On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project 2007 International Conference on Field Programmable Logic and Applications. 10.1109/FPL.2007.4380682. 978-1-4244-1059-0. (415-422).

    http://ieeexplore.ieee.org/document/4380682/

  • Hubner M, Braun L, Becker J, Claus C and Stechele W. Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. Proceedings of the IEEE Computer Society Annual Symposium on VLSI. (41-46).

    https://doi.org/10.1109/ISVLSI.2007.83

  • Becker J and Hübner M. Run-time reconfigurabilility and other future trends. Proceedings of the 19th annual symposium on Integrated circuits and systems design. (9-11).

    https://doi.org/10.1145/1150343.1150346