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- research-articleJanuary 2018
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 11, Issue 1Article No.: 3, Pages 1–23https://doi.org/10.1145/3158229We show that continuously monitoring on-chip delays at the LUT-to-LUT link level during operation allows a field-programmable gate array to detect and self-adapt to aging and environmental timing effects. Using a lightweight (<4% added area) mechanism ...
- research-articleFebruary 2017
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays
FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 85–94https://doi.org/10.1145/3020078.3026124How should we perform component-specific adaptation for FPGAs? Prior work has demonstrated that the negative effects of variation can be largely mitigated using complete knowledge of device characteristics and full per-FPGA CAD flow. However, the cost ...
- short-paperFebruary 2016
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement
FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 100–104https://doi.org/10.1145/2847263.2847334Recent work shows how to use on-chip structures to measure the fabricated delays of fine-grained resources on modern FPGAs. We show that simultaneous measurement of multiple, disjoint paths will result in different measured delays from isolated ...
- research-articleDecember 2014
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Issue 4Article No.: 32, Pages 1–23https://doi.org/10.1145/2597889Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and ...
- ArticleMay 2014
GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction
With continued scaling, all transistors are no longer created equal. The delay of a length 4 horizontal routing segment at coordinates (23,17) will differ from one at (12,14) in the sameFPGA and from the same segment in another FPGA. The vendor tools ...
- research-articleFebruary 2013
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 81–90https://doi.org/10.1145/2435264.2435281Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and ...
- research-articleFebruary 2011
Crystals and Snowflakes: Building Computation from Nanowire Crossbars
Suitable architectures and paradigm shifts in assembly and usage models will make it possible to exploit the compactness and energy benefits of single-nanometer dimension devices and allow extending these structures into the third dimension without ...
- articleJuly 2005
Evaluation of design strategies for stochastically assembled nanoarray memories
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 1, Issue 2Pages 73–108https://doi.org/10.1145/1084748.1084749A key challenge facing nanotechnologies is learning to control uncertainty introduced by stochastic self-assembly. In this article, we explore architectural and manufacturing strategies to cope with this uncertainty when assembling nanoarrays, crossbars ...
- ArticleMay 2005
Analysis of a Mask-Based Nanowire Decoder
ISVLSI '05: Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI DesignPages 6–13https://doi.org/10.1109/ISVLSI.2005.17A key challenge facing nanotechnologies will be controlling nanoarrays, two orthogonal sets of nanowires that form a crossbar, using a moderate number of mesoscale wires. Three methods have been proposed to use mesoscale wires to control individual ...