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Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays

Authors:

Benjamin Gojman,

André DeHonAuthors Info & Claims

FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 85 - 94

https://doi.org/10.1145/3020078.3026124

Published: 22 February 2017 Publication History

Abstract

How should we perform component-specific adaptation for FPGAs? Prior work has demonstrated that the negative effects of variation can be largely mitigated using complete knowledge of device characteristics and full per-FPGA CAD flow. However, the cost of per-FPGA characterization and mapping could be prohibitively expensive. We explore light-weight options for per-FPGA mapping that avoid the need for a priori device characterization and perform less expensive per FPGA customization work. We characterize the tradeoff between Quality-of-Results (energy, delay) and per-device mapping costs for 7 design points ranging from complete mapping based on knowledge to no per-device mapping. We show that it is possible to get 48-77% of the component-specific mapping delay benefit or 57% of the energy benefit with a mapping that takes less than 20 seconds per FPGA. An incremental solution can start execution after a 21 ms bitstream load and converge to 77% delay benefit after 18 seconds of runtime.

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Cited By

Hassani FSadrosadati MRohbani NPointner SWille RSarbazi-azad H(2024)An Efficient FPGA Architecture with Turn-Restricted Switch BoxesACM Transactions on Design Automation of Electronic Systems10.1145/3643809Online publication date: 3-Feb-2024
https://doi.org/10.1145/3643809
Serajeh-hassani FSadrosadati MPointner SWille RSarbazi-azad H(2019)Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00115(615-620)Online publication date: Jul-2019
https://doi.org/10.1109/ISVLSI.2019.00115
Giesen HGojman BRubin RKim JDehon A(2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
https://dl.acm.org/doi/10.1145/3158229
Show More Cited By

Index Terms

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays
1. Hardware

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cover image ACM Conferences

FPGA '17: Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2017

312 pages

ISBN:9781450343541

DOI:10.1145/3020078

General Chair:
Jonathan Greene
Microsemi, USA
,
Program Chair:
Jason H. Anderson
University of Toronto, Canada

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 22 February 2017

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Leggett Family Fellowship
DARPA

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FPGA '17

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SIGDA

FPGA '17: The 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 22 - 24, 2017

California, Monterey, USA

Acceptance Rates

FPGA '17 Paper Acceptance Rate 25 of 101 submissions, 25%;

Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Hassani FSadrosadati MRohbani NPointner SWille RSarbazi-azad H(2024)An Efficient FPGA Architecture with Turn-Restricted Switch BoxesACM Transactions on Design Automation of Electronic Systems10.1145/3643809Online publication date: 3-Feb-2024
https://doi.org/10.1145/3643809
Serajeh-hassani FSadrosadati MPointner SWille RSarbazi-azad H(2019)Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00115(615-620)Online publication date: Jul-2019
https://doi.org/10.1109/ISVLSI.2019.00115
Giesen HGojman BRubin RKim JDehon A(2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
https://dl.acm.org/doi/10.1145/3158229
Giesen HRubin RGojman BDeHon A(2017)Self-Adaptive Timing RepairIEEE Design & Test10.1109/MDAT.2017.275091234:6(54-62)Online publication date: Dec-2017
https://doi.org/10.1109/MDAT.2017.2750912

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