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- research-articleOctober 2024
A Parallel Hash Table for Streaming Applications
PACT '24: Proceedings of the 2024 International Conference on Parallel Architectures and Compilation TechniquesPages 297–308https://doi.org/10.1145/3656019.3676951Hash Tables are important data structures for a wide range of data intensive applications in various domains. They offer compact storage for sparse data, but their performance has difficulties to scale with the rapidly increasing volumes of data as they ...
- research-articleJune 2023
Stream Aggregation with Compressed Sliding Windows
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 16, Issue 3Article No.: 37, Pages 1–28https://doi.org/10.1145/3590774High performance stream aggregation is critical for many emerging applications that analyze massive volumes of data. Incoming data needs to be stored in a sliding window during processing, in case the aggregation functions cannot be computed ...
- invited-talkAugust 2023
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
- Lluc Alvarez,
- Abraham Ruiz,
- Arnau Bigas-Soldevilla,
- Pavel Kuroedov,
- Alberto Gonzalez,
- Hamsika Mahale,
- Noe Bustamante,
- Albert Aguilera,
- Francesco Minervini,
- Javier Salamero,
- Oscar Palomar,
- Vassilis Papaefstathiou,
- Antonis Psathakis,
- Nikolaos Dimou,
- Michalis Giaourtas,
- Iasonas Mastorakis,
- Georgios Ieronymakis,
- Georgios-Michail Matzouranis,
- Vasilis Flouris,
- Nick Kossifidis,
- Manolis Marazakis,
- Bhavishya Goel,
- Madhavan Manivannan,
- Ahsen Ejaz,
- Panagiotis Strikos,
- Mateo Vázquez,
- Ioannis Sourdis,
- Pedro Trancoso,
- Per Stenström,
- Jens Hagemeyer,
- Lennart Tigges,
- Nils Kucza,
- Jean-Marc Philippe,
- Ioannis Papaefstathiou
CF '23: Proceedings of the 20th ACM International Conference on Computing FrontiersPages 309–314https://doi.org/10.1145/3587135.3592178The eProcessor project aims at creating a RISC-V full stack ecosystem. The eProcessor architecture combines a high-performance out-of-order core with energy-efficient accelerators for vector processing and artificial intelligence with reduced-precision ...
- research-articleJanuary 2023
FlatPack: Flexible Compaction of Compressed Memory
PACT '22: Proceedings of the International Conference on Parallel Architectures and Compilation TechniquesPages 96–108https://doi.org/10.1145/3559009.3569653The capacity and bandwidth of main memory is an increasingly important factor in computer system performance. Memory compression and compaction have been combined to increase effective capacity and reduce costly page faults. However, existing systems ...
- research-articleJanuary 2022
L2C: Combining Lossy and Lossless Compression on Memory and I/O
ACM Transactions on Embedded Computing Systems (TECS), Volume 21, Issue 1Article No.: 12, Pages 1–27https://doi.org/10.1145/3481641In this article, we introduce L2C, a hybrid lossy/lossless compression scheme applicable both to the memory subsystem and I/O traffic of a processor chip. L2C employs general-purpose lossless compression and combines it with state-of-the-art lossy ...
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- research-articleFebruary 2021
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers
IEEE/ACM Transactions on Networking (TON), Volume 29, Issue 1Pages 318–331https://doi.org/10.1109/TNET.2020.3034581This paper describes HighwayNoC, a Network-on-chip (NoC) that approaches ideal network performance using a Dual Data Rate (DDR) datapath. Based on the observation that routers datapath is faster than control, a DDR NoC allows flits to be routed at DDR ...
- research-articleNovember 2020
MemSZ: Squeezing Memory Traffic with Lossy Compression
ACM Transactions on Architecture and Code Optimization (TACO), Volume 17, Issue 4Article No.: 40, Pages 1–25https://doi.org/10.1145/3424668This article describes Memory Squeeze (MemSZ), a new approach for lossy general-purpose memory compression. MemSZ introduces a low latency, parallel design of the Squeeze (SZ) algorithm offering aggressive compression ratios, up to 16:1 in our ...
- research-articleAugust 2019
AVR: Reducing Memory Traffic with Approximate Value Reconstruction
ICPP '19: Proceedings of the 48th International Conference on Parallel ProcessingArticle No.: 4, Pages 1–10https://doi.org/10.1145/3337821.3337824This paper describes Approximate Value Reconstruction (AVR), an architecture for approximate memory compression. AVR reduces the memory traffic of applications that tolerate approximations in their dataset. Thereby, it utilizes more efficiently the ...
- research-articleJanuary 2019
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 65, Pages 1–23https://doi.org/10.1145/3293447DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of applications capitalizing on advances of 3D-stacking technology; however, they are still far from their ideal performance. Besides the unavoidable DRAM ...
- research-articleJanuary 2019
Energy-Efficient Runtime Management of Heterogeneous Multicores using Online Projection
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 63, Pages 1–26https://doi.org/10.1145/3293446Heterogeneous multicores offer flexibility in the form of different core types and Dynamic Voltage and Frequency Scaling (DVFS), defining a vast configuration space. The optimal configuration choice is not always straightforward, even for single ...
- research-articleOctober 2018
FreewayNoC: a DDR NoC with pipeline bypassing
NOCS '18: Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-ChipArticle No.: 8, Pages 1–8This paper introduces FreewayNoC, a Network-on-chip that routes packets at Dual Data Rate (DDR) and allows pipeline bypassing. Based on the observation that routers datapath is faster than control, a recent NoC design allowed flits to be routed at DDR ...
- research-articleJune 2018
DDRNoC: Dual Data-Rate Network-on-Chip
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 2Article No.: 25, Pages 1–24https://doi.org/10.1145/3200201This article introduces DDRNoC, an on-chip interconnection network capable of routing packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal),...
- research-articleOctober 2017
Odd-ECC: on-demand DRAM error correcting codes
MEMSYS '17: Proceedings of the International Symposium on Memory SystemsPages 96–111https://doi.org/10.1145/3132402.3132443An application may have different sensitivity to faults in different subsets of the data it uses. Some data regions may therefore be more critical than others. Capitalizing on this observation, Odd-ECC provides a mechanism to dynamically select the ...
- research-articleOctober 2016
Runtime management of adaptive MPSoCs for graceful degradation
CASES '16: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded SystemsArticle No.: 5, Pages 1–10https://doi.org/10.1145/2968455.2968517In this paper we propose optimization algorithms for the runtime management of gracefully degradable adaptive MP-SoCs. Assuring the reliability of all hardware components in a system becomes increasingly difficult. On top of the growing defect densities ...
- research-articleMay 2016
Secure key-exchange protocol for implants using heartbeats
CF '16: Proceedings of the ACM International Conference on Computing FrontiersPages 119–126https://doi.org/10.1145/2903150.2903165The cardiac interpulse interval (IPI) has recently been proposed to facilitate key exchange for implantable medical devices (IMDs) using a patient's own heartbeats as a source of trust. While this form of key exchange holds promise for IMD security, its ...
- research-articleMarch 2016
ECOSCALE: reconfigurable computing and runtime system for future exascale systems
- Iakovos Mavroidis,
- Ioannis Papaefstathiou,
- Luciano Lavagno,
- Dimitrios S. Nikolopoulos,
- Dirk Koch,
- John Goodacre,
- Ioannis Sourdis,
- Vassilis Papaefstathiou,
- Marcello Coppola,
- Manuel Palomino
In order to reach exascale performance, current HPC systems need to be improved. Simple hardware scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation ...
- research-articleFebruary 2016
RQNoC: A Resilient Quality-of-Service Network-on-Chip with Service Redirection
ACM Transactions on Embedded Computing Systems (TECS), Volume 15, Issue 2Article No.: 28, Pages 1–25https://doi.org/10.1145/2846097In this article, we describe RQNoC, a service-oriented Network-on-Chip (NoC) resilient to permanent faults. We characterize the network resources based on the particular service that they support and, when faulty, bypass them, allowing the respective ...
- articleJanuary 2016
Resilient Chip Multiprocessors with Mixed-Grained Reconfigurability
This article presents a chip multiprocessor (CMP) design that mixes coarse- and fine-grained reconfigurability to increase core availability of safety-critical embedded systems in the presence of hard errors. The authors conducted a comprehensive design-...
- ArticleAugust 2015
On Using a Von Neumann Extractor in Heart-Beat-Based Security
The Inter-Pulse-Interval (IPI) of heart beats has previously been suggested for facilitating security in mobile health (mHealth) applications. In heart-beat-based security, a security key is derived from the time difference between consecutive heart ...