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SPORE: Combining Symmetry and Partial Order Reduction
Proceedings of the ACM on Programming Languages (PACMPL), Volume 8, Issue PLDIArticle No.: 219, Pages 1781–1803https://doi.org/10.1145/3656449Symmetry reduction (SR) and partial order reduction (POR) aim to scale up model checking by exploiting the underlying program structure: SR avoids exploring executions equivalent up to some permutation of symmetric threads, while POR avoids exploring ...
- research-articleMay 2024
Challenges in Empirically Testing Memory Persistency Models
ICSE-NIER'24: Proceedings of the 2024 ACM/IEEE 44th International Conference on Software Engineering: New Ideas and Emerging ResultsApril 2024, Pages 82–86https://doi.org/10.1145/3639476.3639765Memory persistency models provide the foundational rules for software engineers to develop applications that take advantage of non-volatile memory (NVM), dictating which (and when) writes to NVM are deemed persistent. Though formalised for Intel-x86 and ...
- ArticleApril 2024
Specifying and Verifying Persistent Libraries
AbstractWe present a general framework for specifying and verifying persistent libraries, that is, libraries of data structures that provide some persistency guarantees upon a failure of the machine they are executing on. Our framework enables modular ...
- ArticleApril 2024
Enhancing GenMC’s Usability and Performance
Tools and Algorithms for the Construction and Analysis of SystemsApr 2024, Pages 66–84https://doi.org/10.1007/978-3-031-57249-4_4AbstractGenMC is a state-of-the-art stateless model checker that can verify safety properties of concurrent C/C++ programs under a wide range of memory consistency models, such as SC, TSO, RC11, and IMM.
In this paper, we improve the performance and ...
- ArticleJuly 2023
Unblocking Dynamic Partial Order Reduction
AbstractExisting dynamic partial order reduction (DPOR) algorithms scale poorly on concurrent data structure benchmarks because they visit a huge number of blocked executions due to spinloops.
In response, we develop Awamoche, a sound, complete, and ...
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- ArticleApril 2023
Reconciling Preemption Bounding with DPOR
Tools and Algorithms for the Construction and Analysis of SystemsApr 2023, Pages 85–104https://doi.org/10.1007/978-3-031-30823-9_5AbstractThere are two major techniques for scaling up stateless model checking: dynamic partial order reduction (DPOR), which only explores executions that differ in the ordering of racy accesses, and preemption bounding, which only explores executions ...
- research-articleJanuary 2023
AtoMig: Automatically Migrating Millions Lines of Code from TSO to WMM
- Martin Beck,
- Koustubha Bhat,
- Lazar Stričević,
- Geng Chen,
- Diogo Behrens,
- Ming Fu,
- Viktor Vafeiadis,
- Haibo Chen,
- Hermann Härtig
ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2January 2023, Pages 61–73https://doi.org/10.1145/3575693.3579849CPUs with weak memory-consistency models (WMMs), such as Arm and RISC-V, are rapidly increasing their market share. Porting legacy x86 applications to such CPUs requires introducing extra synchronization to prevent WMM-related concurrency bugs---a ...
- research-articleJanuary 2023
The Path to Durable Linearizability
Proceedings of the ACM on Programming Languages (PACMPL), Volume 7, Issue POPLArticle No.: 26, Pages 748–774https://doi.org/10.1145/3571219There is an increasing body of literature proposing new and efficient persistent versions of concurrent data structures ensuring that a consistent state can be recovered after a power failure or a crash. Their correctness is typically stated in terms of ...
Kater: Automating Weak Memory Model Metatheory and Consistency Checking
Proceedings of the ACM on Programming Languages (PACMPL), Volume 7, Issue POPLArticle No.: 19, Pages 544–572https://doi.org/10.1145/3571212The metatheory of axiomatic weak memory models covers questions like the correctness of compilation mappings from one model to another and the correctness of local program transformations according to a given model---topics usually requiring lengthy ...
Model checking for a multi-execution memory model
Proceedings of the ACM on Programming Languages (PACMPL), Volume 6, Issue OOPSLA2Article No.: 152, Pages 758–785https://doi.org/10.1145/3563315Multi-execution memory models, such as Promising and Weakestmo, are an advanced class of weak memory consistency models that justify certain outcomes of a concurrent program by considering multiple candidate executions collectively. While this key ...
- ArticleFebruary 2023
SMT-Based Verification of Persistency Invariants of Px86 Programs
Verified Software. Theories, Tools and Experiments.Oct 2022, Pages 92–110https://doi.org/10.1007/978-3-031-25803-9_6AbstractWhile non-volatile memory (NVM) promises to be both performant and durable, the semantics provided by the hardware architectures are rather subtle and significantly complicate reasoning about the possible observed state after a crash.
Starting from ...
Truly stateless, optimal dynamic partial order reduction
Proceedings of the ACM on Programming Languages (PACMPL), Volume 6, Issue POPLArticle No.: 49, Pages 1–28https://doi.org/10.1145/3498711Dynamic partial order reduction (DPOR) verifies concurrent programs by exploring all their interleavings up to some equivalence relation, such as the Mazurkiewicz trace equivalence. Doing so involves a complex trade-off between space and time. Existing ...
Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores
Proceedings of the ACM on Programming Languages (PACMPL), Volume 6, Issue POPLArticle No.: 22, Pages 1–31https://doi.org/10.1145/3498683Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the consistency semantics of multi-threaded programs as well as the persistency semantics of programs interfacing ...
Making weak memory models fair
Proceedings of the ACM on Programming Languages (PACMPL), Volume 5, Issue OOPSLAArticle No.: 98, Pages 1–27https://doi.org/10.1145/3485475Liveness properties, such as termination, of even the simplest shared-memory concurrent programs under sequential consistency typically require some fairness assumptions about the scheduler. Under weak memory models, we observe that the standard notions ...
- ArticleJuly 2021
GenMC: A Model Checker for Weak Memory Models
AbstractGenMC is an LLVM-based state-of-the-art stateless model checker for concurrent C/C++ programs. Its modular infrastructure allows it to support complex memory models, such as RC11 and IMM, and makes it easy to extend to support further axiomatic ...
- ArticleMay 2021
Verifying and Optimizing the HMCS Lock for Arm Servers
AbstractTo optimize the performance of some of our systems running on non-uniform memory architecture (NUMA) servers with Arm processors, we have implemented multiple versions of the HMCS lock, an advanced NUMA-aware lock that has been identified in the ...
- ArticleMay 2021
BAM: Efficient Model Checking for Barriers
AbstractStateless Model Checking (SMC) and Dynamic Partial Order Reduction (DPOR) are prominent techniques that are often used together to verify safety properties of concurrent programs under a variety of different memory models. Although existing SMC/...
- research-articleApril 2021
VSync: push-button verification and optimization for synchronization primitives on weak memory models
- Jonas Oberhauser,
- Rafael Lourenco de Lima Chehab,
- Diogo Behrens,
- Ming Fu,
- Antonio Paolillo,
- Lilith Oberhauser,
- Koustubha Bhat,
- Yuzhong Wen,
- Haibo Chen,
- Jaeho Kim,
- Viktor Vafeiadis
ASPLOS '21: Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating SystemsApril 2021, Pages 530–545https://doi.org/10.1145/3445814.3446748Implementing highly efficient and correct synchronization primitives on modern Weak Memory Model (WMM) architectures, such as ARM and RISC-V, is very difficult even for human experts. We introduce VSync, a framework to assist in optimizing and verifying ...
- ArticleMarch 2021
The Decidability of Verification under PS 2.0
AbstractWe consider the reachability problem for finite-state multi-threaded programs under the promising semantics (PS 2.0) of Lee et al., which captures most common program transformations. Since reachability is already known to be undecidable in the ...
- research-articleJanuary 2021
PerSeVerE: persistency semantics for verification under ext4
Proceedings of the ACM on Programming Languages (PACMPL), Volume 5, Issue POPLArticle No.: 43, Pages 1–29https://doi.org/10.1145/3434324Although ubiquitous, modern filesystems have rather complex behaviours that are hardly understood by programmers and lead to severe software bugs such as data corruption. As a first step to ensure correctness of software performing file I/O, we formalize ...