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- research-articleAugust 2022
Improving compute in-memory ECC reliability with successive correction
- Brian Crafton,
- Zishen Wan,
- Samuel Spetalnick,
- Jong-Hyeok Yoon,
- Wei Wu,
- Carlos Tokunaga,
- Vivek De,
- Arijit Raychowdhury
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation ConferenceJuly 2022, Pages 745–750https://doi.org/10.1145/3489517.3530526Compute in-memory (CIM) is an exciting technique that minimizes data transport, maximizes memory throughput, and performs computation on the bitline of memory sub-arrays. This is especially interesting for machine learning applications, where increased ...
- research-articleNovember 2021
Advances in Microprocessor Cache Architectures Over the Last 25 Years
- Ravi Iyer,
- Vivek De,
- Ramesh Illikkal,
- David Koufaty,
- Bhushan Chitlur,
- Andrew Herdrich,
- Muhammad Khellah,
- Fatih Hamzaoglu,
- Eric Karl
IEEE Micro (IMIC), Volume 41, Issue 6Nov.-Dec. 2021, Pages 78–88https://doi.org/10.1109/MM.2021.3114903Over the last 25 years, the use of caches has advanced significantly in mainstream microprocessors to address the memory wall challenge. As we transformed microprocessors from single-core to multicore to manycore, innovations in the architecture, design, ...
- research-articleMay 2021
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities
- Sriram Vangal,
- Somnath Paul,
- Steven Hsu,
- Amit Agarwal,
- Saurabh Kumar,
- Ram Krishnamurthy,
- Harish Krishnamurthy,
- James Tschanz,
- Vivek De,
- Chris H. Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 29, Issue 5May 2021, Pages 843–856https://doi.org/10.1109/TVLSI.2021.3061649The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and applications, ...
- research-articleAugust 2016
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines
ISLPED '16: Proceedings of the 2016 International Symposium on Low Power Electronics and DesignAugust 2016, Pages 130–135https://doi.org/10.1145/2934583.2934607This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of encryption engines. We propose security aware design modes for low passive FIVR to improve robustness of an encryption-...
- tutorialNovember 2015
Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided DesignNovember 2015, Pages 159–164Circuit and design techniques for fine-grain power management in manycore System-on-Chip (SoC) are presented. Recent advances in dynamic platform control techniques to enable (1) independent voltage-frequency domains, (2) dynamic power budget allocation ...
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- research-articleNovember 2015
Fine-grain power management in manycore processor and System-on-Chip (SoC) designs
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)Pages 159–164https://doi.org/10.1109/ICCAD.2015.7372564Circuit and design techniques for fine-grain power management in manycore System-on-Chip (SoC) are presented. Recent advances in dynamic platform control techniques to enable (1) independent voltage-frequency domains, (2) dynamic power budget allocation ...
- research-articleSeptember 2015
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 12, Issue 3Article No.: 21, Pages 1–19https://doi.org/10.1145/2746341Traditional synchronous VLSI design requires that all computations in a logic stage complete in one clock cycle. This leads to increasingly pessimistic design as technology scaling introduces increasingly significant parametric variations that result in ...
- abstractJune 2013
Circuits for resilient systems
FTXS '13: Proceedings of the 3rd Workshop on Fault-tolerance for HPC at extreme scaleJune 2013, Pages 11–12https://doi.org/10.1145/2465813.2465815Timing and functional failures caused by process, voltage and temperature (PVT) variations pose major challenges to achieving energy-efficient performance in multi-core & many-core processor designs in nanoscale CMOS. Radiation-induced soft errors and ...
- research-articleMarch 2013
Near-threshold voltage design in nanoscale CMOS
DATE '13: Proceedings of the Conference on Design, Automation and Test in EuropeMarch 2013, Page 612Near-Threshold Voltage (NTV) operation of a CMOS design is defined as the voltage-frequency operating point where the energy consumed per compute operation (pJ/op) reaches a minimum, or the energy efficiency (Mops/Watt) peaks. Typically, this operating ...
- research-articleMarch 2012
Design for test and reliability in ultimate CMOS
- Michael Nicolaidis,
- Lorena Anghel,
- Yervant Zorian,
- Tanay Karnik,
- Keith Bowman,
- James Tschanz,
- Shih-Lien Lu,
- Carlos Tokunaga,
- Arijit Raychowdhury,
- Muhammad Khellah,
- Jaydeep Kulkarni,
- Vivek De,
- Dimiter Avresky
DATE '12: Proceedings of the Conference on Design, Automation and Test in EuropeMarch 2012, Pages 677–682This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and ...
- opinionMarch 2011
Editorial
- Yehea I. Ismail,
- Massimo Alioto,
- Elad Alon,
- Mohab Anis,
- Tawfik Arabi,
- Iris Bahar,
- Valeriu Beiu,
- Sanjukta Bhanja,
- Chirn Chye Boon,
- Chaitali Chakrabarti,
- Chip-Hong Chang,
- Jonathan Chang,
- Robert Chen-Hao Chang,
- Deming Chen,
- Poki Chen,
- Pasquale Corsonello,
- Vivek De,
- Sang H. Dhong,
- Robert Dick,
- Nikil D. Dutt,
- Maged Ghoneima,
- Patrick Girard,
- Dimitris Gizopoulos,
- Peter Gregorius,
- Pavan Kumar Hanumolu,
- Mona Mostafa Hella,
- Mohammed Ismail,
- Rajiv V. Joshi,
- Tanay Karnik,
- Chulwoo Kim,
- Ram K. Krishnamurthy,
- Nasser A. Kurd,
- Volkan Kursun,
- Mohammad M. Mansour,
- Malgorzata Marek-Sadowska,
- Yehia Massoud,
- Pramod Kumar Meher,
- Chris J. Myers,
- Seda Ogrenci Memik,
- Sule Ozev,
- David Z. Pan,
- Zebo Peng,
- Emre Salman,
- Li Shang,
- Ankur Srivastava,
- Sying-Jyan Wang,
- Zhongfeng Wang,
- Yuan Xie,
- Jiang Xu,
- Hai Zhou,
- Stacey Weber Jackson
- short-paperAugust 2010
Resilient microprocessor design for high performance & energy efficiency
- Keith A. Bowman,
- James W. Tschanz,
- Shih-Lien L. Lu,
- Paolo A. Aseron,
- Muhammad M. Khellah,
- Arijit Raychowdhury,
- Bibiche M. Geuskens,
- Carlos Tokunaga,
- Chris B. Wilkerson,
- Tanay Karnik,
- Vivek K. De
ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and designAugust 2010, Pages 355–356https://doi.org/10.1145/1840845.1840919Conventional microprocessors require a clock frequency (FCLK) guardband to ensure correct functionality during infrequent dynamic operating variations in supply voltage (VCC), temperature, and transistor aging. Consequently, these inflexible designs ...
- research-articleJanuary 2010
Resilient design in scaled CMOS for energy efficiency
- James Tschanz,
- Keith Bowman,
- Muhammad Khellah,
- Chris Wilkerson,
- Bibiche Geuskens,
- Dinesh Somasekhar,
- Arijit Raychowdhury,
- Jaydeep Kulkarni,
- Carlos Tokunaga,
- Shih-Lien Lu,
- Tanay Karnik,
- Vivek De
ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation ConferenceJanuary 2010, Page 625Traditional processors are designed to guarantee error-free operation under worst-case (1) device & interconnect parameter variations resulting from less than ideal manufacturing process control; (2) static & erratic defects; (3) operating environments ...
- articleNovember 2009
SRAM dynamic stability estimation using MPFP and its applications
Microelectronics Journal (MICROJ), Volume 40, Issue 11November, 2009, Pages 1523–1530https://doi.org/10.1016/j.mejo.2009.01.015In this paper, an accurate approach for estimating the dynamic stability of static random access memory (SRAM) is proposed. The conventional methods of SRAM stability estimation suffer from two major drawbacks: (1) using static failure criteria, such as ...
- articleSeptember 2009
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCSPI), Volume 56, Issue 9September 2009, Pages 2020–2032https://doi.org/10.1109/TCSI.2008.2010155As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional ...
- research-articleJuly 2009
Circuit techniques for dynamic variation tolerance
DAC '09: Proceedings of the 46th Annual Design Automation ConferenceJuly 2009, Pages 4–7https://doi.org/10.1145/1629911.1629915Three circuit techniques for dynamic variation tolerance are presented: (i) Sensors with adaptive voltage and frequency circuits, (ii) Tunable replica circuits for timing-error prediction with error recovery, and (iii) Embedded error-detection ...
- articleFebruary 2009
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers (TCSPI), Volume 56, Issue 2February 2009, Pages 384–394https://doi.org/10.1109/TCSI.2008.2001805In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in "many-core" SoCs and in 3-...
- research-articleDecember 2008
Accurate estimation of SRAM dynamic stability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 16, Issue 12December 2008, Pages 1639–1647https://doi.org/10.1109/TVLSI.2008.2001941In this paper, an accurate approach for estimating SRAM dynamic stability is proposed. The conventional methods of SRAM stability estimation suffer from two major drawbacks: 1) using static failure criteria, such as static noise margin (SNM), which does ...
- research-articleNovember 2008
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design
ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided DesignNovember 2008, Pages 270–277For the first time, a new source of random threshold voltage (Vth) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of variability, ...