Article

Interconnect capacitance estimation for FPGAs

Authors:

Jason H. Anderson,

Farid N. NajmAuthors Info & Claims

ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Pages 713 - 718

Published: 27 January 2004 Publication History

Abstract

The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and develop an empirical estimation model, suitable for use in power-aware placement, early power prediction, and other applications. We show that estimation accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also show that there is an inherent variability (noise) in the capacitance of nets routed using a commercial FPGA layout tool. This variability limits the accuracy attainable in capacitance estimation. Experimental results show that the proposed estimation model works well given the noise limitations.

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Cited By

Giechaskiel IEguro KRasmussen K(2019)Leakier WiresACM Transactions on Reconfigurable Technology and Systems10.1145/332248312:3(1-29)Online publication date: 23-Aug-2019
https://dl.acm.org/doi/10.1145/3322483
Giechaskiel IRasmussen KEguro KKim JAhn GKim SKim YLopez JKim T(2018)Leaky WiresProceedings of the 2018 on Asia Conference on Computer and Communications Security10.1145/3196494.3196518(15-27)Online publication date: 29-May-2018
https://dl.acm.org/doi/10.1145/3196494.3196518
Jevtic RCarreras CPejovic VCheng CReda S(2009)Floorplan-based FPGA interconnect power estimation in DSP circuitsProceedings of the 11th international workshop on System level interconnect prediction10.1145/1572471.1572481(53-60)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1572471.1572481
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Interconnect capacitance estimation for FPGAs
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Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

January 2004

957 pages

ISBN:0780381750

General Chair:
Masaharu Imai
Osaka University

Sponsors

IPSJ: Information Processing Society of Japan
IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE: Institute of Electronics, Information and Communication Engineers

Publisher

IEEE Press

Publication History

Published: 27 January 2004

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Conference

ASPDAC04

Sponsor:

IPSJ
SIGDA
IEICE

ASPDAC04: Asia and South Pacific Design Automation Conference 2004

January 27 - 30, 2004

Yokohama, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

Giechaskiel IEguro KRasmussen K(2019)Leakier WiresACM Transactions on Reconfigurable Technology and Systems10.1145/332248312:3(1-29)Online publication date: 23-Aug-2019
https://dl.acm.org/doi/10.1145/3322483
Giechaskiel IRasmussen KEguro KKim JAhn GKim SKim YLopez JKim T(2018)Leaky WiresProceedings of the 2018 on Asia Conference on Computer and Communications Security10.1145/3196494.3196518(15-27)Online publication date: 29-May-2018
https://dl.acm.org/doi/10.1145/3196494.3196518
Jevtic RCarreras CPejovic VCheng CReda S(2009)Floorplan-based FPGA interconnect power estimation in DSP circuitsProceedings of the 11th international workshop on System level interconnect prediction10.1145/1572471.1572481(53-60)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1572471.1572481
Reimer ASchulz ANebel WNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designsProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165609(151-154)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165609

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