research-article

A novel sequential circuit optimization with clock gating logic

Authors:

Yu-Min Kuo,

Shih-Hung Weng,

Shih-Chieh ChangAuthors Info & Claims

ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Pages 230 - 233

Published: 10 November 2008 Publication History

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Abstract

To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the clock-gating conditions and the next-state function of a Flip-Flop (FF) are correlated and can be used for sequential optimization. We show that the implementation of the next-state function of any FF can be just an inverter if the clock signal is appropriately gated. By exploiting the flexibility between the clock-gating conditions and the next-state function, we propose an iterative optimization technique to minimize the overall timing.

References

[1]

P. Babighian, L. Benini, and E. Macii, "A Scalable Algorithm for RTL Insertion of Gated Clocks Based on ODCs Computation," IEEE Trans. on CAD, vol. 24, no. 1, Jan 2005.

Digital Library

Google Scholar

[2]

M. Alidina, J. Monteiro, S. Devadas, and A. Ghosh, "Precomputation-Based Sequential Logic Optimization for Low Power," Proc. of ICCAD, pp. 74--81, 1994.

Digital Library

Google Scholar

[3]

L. Benini, and G. De Micheli, "Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines," IEEE Trans. on CAD, vol. 15, no. 6, Jun. 1996.

Digital Library

Google Scholar

[4]

M. Müch, B. Wurth, R. Mehra, J. Sproch, and N. When, "Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths," Proc. of DATE, pp. 624--633, 2000.

Digital Library

Google Scholar

[5]

V. Tiwari, S. Malik, and P. Ashar, "Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design," Proc. of ISPLED, pp. 221--226, 1995.

Digital Library

Google Scholar

[6]

H. Kapadia, L. Benini, and G. De Micheli, "Reducing Switching Activity on Datapath Buses with Control-Signal Gating," IEEE J. of Solid-State Circuits, vol. 34, no. 3, March 1999.

Crossref

Google Scholar

[7]

M. Onishi, A. Yamada, H. Noda, and T. Kambe, "A Method of Redundant Clocking Detection and Power Reduction at RT Level Design," Proc. of ISLPED, pp. 131--136, 1997.

Digital Library

Google Scholar

[8]

L. Benini, G. De Micheli, E. Macii, M. Poncino, and R. Scarsi, "Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous Controllers," ACM Trans. on Design Automation Electronic Systems, vol. 4, no. 4, pp. 351--375, 1999.

Digital Library

Google Scholar

[9]

G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and S. Dey, "Common-Case Computation: A High-Level Technique for Power and Performance Optimization," Proc. of DAC, pp 56--61, 1999.

Digital Library

Google Scholar

[10]

Y. Luo, J. Yu, J. Yang, and L. Bhuyan, "Low Power Network Processor Design Using Clock Gating," Proc. of DAC, pp. 13--17, 2005.

Digital Library

Google Scholar

[11]

H. M. Jacobson, "Improved Clock-Gating through Transparent Pipelining," Proc. of ISLPED, pp. 26--31, 2004.

Digital Library

Google Scholar

[12]

N. Banerjee, K. Roy, H. Mahmoodi, and S. Bhunia, "Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating," Proc. of DATE, pp. 6--10, 2006.

Digital Library

Google Scholar

[13]

A. P. Hurst, "Automatic Synthesis of Clock Gating Logic with Controlled Netlist Perturbation," Proc. of DAC, pp. 654--657, 2008

Digital Library

Google Scholar

Cited By

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Bertran RGonzalez MMartorell XNavarro NAyguade EBoku TNakashima HMendelson A(2010)Decomposable and responsive power models for multicore processors using performance countersProceedings of the 24th ACM International Conference on Supercomputing10.1145/1810085.1810108(147-158)Online publication date: 2-Jun-2010
https://dl.acm.org/doi/10.1145/1810085.1810108
Arbel EEisner CRokhlenko O(2009)Resurrecting infeasible clock-gating functionsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629957(160-165)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629957

A novel sequential circuit optimization with clock gating logic
1. Hardware

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Published In

ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

November 2008

855 pages

ISBN:9781424428205

General Chair:
Sani R. Nassif
IBM Austin Research Lab, Austin Texas
,
Program Chair:
Jaijeet Roychowdhury
Univ. of Minnesota, Minneapolis, MN

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IEEE Press

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Published: 10 November 2008

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ASE08

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SIGDA

ASE08: The International Conference on Computer-Aided Design

November 10 - 13, 2008

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Bertran RGonzalez MMartorell XNavarro NAyguade EBoku TNakashima HMendelson A(2010)Decomposable and responsive power models for multicore processors using performance countersProceedings of the 24th ACM International Conference on Supercomputing10.1145/1810085.1810108(147-158)Online publication date: 2-Jun-2010
https://dl.acm.org/doi/10.1145/1810085.1810108
Arbel EEisner CRokhlenko O(2009)Resurrecting infeasible clock-gating functionsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629957(160-165)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629957

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Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic

Clock gating circuit design based on data-driven improvements

Extended sequential logic for synchronous circuit optimization and its applications

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