research-article

Scalable and scalably-verifiable sequential synthesis

Authors:

Alan Mishchenko,

Robert Brayton,

Stephen JangAuthors Info & Claims

ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Pages 234 - 241

Published: 10 November 2008 Publication History

Abstract

This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentially-equivalent nodes. State-encoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an independent inductive prover similar to that used for synthesis, with guaranteed completeness. Experiments with this sequential synthesis show effectiveness. When applied to a set of 20 industrial benchmarks ranging up to 26K registers and up to 53K 6-LUTs, average reductions in register and area are 12.9% and 13.1% respectively while delay is reduced by 1.4%. When applied to the largest academic benchmarks, an average reduction in both registers and area is more than 30%. The associated sequential verification is also scalable and runs about 2x slower than synthesis. The implementation is available in the synthesis and verification system ABC.

References

[1]

J. Baumgartner and A. Kuehlmann, "Min-area retiming on flexible circuit structures", Proc. ICCAD'01, pp. 176--182

Digital Library

[2]

J. Baumgartner, H. Mony, V. Paruthi, R. Kanzelman, and G. Janssen. "Scalable sequential equivalence checking across arbitrary design transformations". Proc. ICCD'06.

[3]

Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. Release 70930. http://www-cad.eecs.berkeley.edu/~alanmi/abc

[4]

A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic model checking without BDDs". Proc. TACAS '99, pp. 193--207.

Digital Library

[5]

P. Bjesse and K. Claessen. "SAT-based verification without state space traversal". Proc. FMCAD'00. LNCS, Vol. 1954, pp. 372--389.

Digital Library

[6]

P. Bjesse and J. Kukula, "Automatic generalized phase abstraction for formal verification", Proc. ICCAD'06, pp. 1076--1082.

Digital Library

[7]

S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", Proc. ICCAD '05, pp. 519--526.

Digital Library

[8]

J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE Trans. CAD, vol. 13(1), January 1994, pp. 1--12.

Digital Library

[9]

N. Een and N. Sörensson, "An extensible SAT-solver". SAT '03. http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat

[10]

C. A. J. van Eijk. Sequential equivalence checking based on structural similarities, IEEE TCAD, 19(7), July 2000, pp. 814--819.

Digital Library

[11]

IWLS 2005 Benchmarks. http://iwls.org/iwls2005/benchmarks.html

[12]

J.-H. Jiang and R. Brayton, "Retiming and resynthesis: A complexity perspective". IEEE TCAD, Vol. 25 (12), Dec. 2006, pp. 2674--2686.

Digital Library

[13]

J.-H. Jiang and W.-L. Hung, "Inductive equivalence checking under retiming and resynthesis", Proc. ICCAD'07, pp. 326--333

Digital Library

[14]

A. Kuehlmann, "Dynamic transition relation simplification for bounded property checking". Proc. ICCAD '04, pp. 50--57.

Digital Library

[15]

B. Lin and A. R. Newton, "Exact removal of redundant state registers using Binary Decision Diagrams," Proc. IFIP TC 10/WG 10.5 Intl Conf. VLSI '91, Edinburgh, Scotland, pp. 277--286.

[16]

F. Lu, L. Wang, K. Cheng, J. Moondanos, and Z. Hanna, "A signal correlation guided ATPG solver and its applications for solving difficult industrial cases," Proc. DAC '03, pp. 668--673.

Digital Library

[17]

F. Lu and T. Cheng. "IChecker: An efficient checker for inductive invariants". Proc. HLDVT '06, pp. 176--180.

[18]

K. L. McMillan. "Interpolation and SAT-Based model checking". Proc. CAV'03, pp. 1--13

[19]

A. Mishchenko, S. Chatterjee, R. Jiang, and R. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification", ERL Technical Report, EECS Dept., U. C. Berkeley, March 2005.

[20]

A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een, "Improvements to combinational equivalence checking", Proc. ICCAD '06, pp. 836--843

Digital Library

[21]

A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. ICCAD '07.

Digital Library

[22]

A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC '06, pp. 532--536.

Digital Library

[23]

H. Mony, J. Baumgartner, V. Paruthi, and R. Kanzelman. "Exploiting suspected redundancy without proving it". Proc. DAC'05.

Digital Library

[24]

P. Pan and C.-C. Lin, "A new retiming-based technology mapping algorithm for LUT-based FPGAs," Proc. FPGA '98, pp. 35--42.

Digital Library

[25]

E. Sentovich et al. "SIS: A system for sequential circuit synthesis". Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, UC Berkeley, 1992.

[26]

E. M. Sentovich, H. Toma, and G. Berry, "Efficient latch optimization using exclusive sets", Proc. DAC'97, pp. 8--11.

Digital Library

[27]

http://www.eecs.berkeley.edu/~alanmi/publications/other/vss.pdf

Cited By

Zaraket FJaber MNoureddine MFalcone Y(2019)From high-level modeling toward efficient and trustworthy circuitsInternational Journal on Software Tools for Technology Transfer (STTT)10.1007/s10009-017-0462-521:2(143-163)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s10009-017-0462-5
Chandrasekharan ASoeken MGroße DDrechsler R(2016)Precise error determination of approximated components in sequential circuits with model checkingProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898069(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898069
Chen LEbrahimi MTahoori M(2015)Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control PathsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5519-331:2(193-206)Online publication date: 1-Apr-2015
https://dl.acm.org/doi/10.1007/s10836-015-5519-3
Show More Cited By

Recommendations

System Synthesis with VHDL: A Transformational Approach
Can reactive synthesis and syntax-guided synthesis be friends?
SPLASH Companion 2021: Companion Proceedings of the 2021 ACM SIGPLAN International Conference on Systems, Programming, Languages, and Applications: Software for Humanity

While reactive synthesis and syntax-guided synthesis (SyGuS) have seen enormous progress in recent years, combining the two approaches has remained a challenge. In this work, we present the synthesis of reactive programs from Temporal Stream Logic ...
Sequential circuit synthesis at the gate level

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '08: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

November 2008

855 pages

ISBN:9781424428205

General Chair:
Sani R. Nassif
IBM Austin Research Lab, Austin Texas
,
Program Chair:
Jaijeet Roychowdhury
Univ. of Minnesota, Minneapolis, MN

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)
IEEE CASS/CANDE

Publisher

IEEE Press

Publication History

Published: 10 November 2008

Check for updates

Qualifiers

Research-article

Conference

ASE08

Sponsor:

SIGDA

ASE08: The International Conference on Computer-Aided Design

November 10 - 13, 2008

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
191
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 11 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Zaraket FJaber MNoureddine MFalcone Y(2019)From high-level modeling toward efficient and trustworthy circuitsInternational Journal on Software Tools for Technology Transfer (STTT)10.1007/s10009-017-0462-521:2(143-163)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s10009-017-0462-5
Chandrasekharan ASoeken MGroße DDrechsler R(2016)Precise error determination of approximated components in sequential circuits with model checkingProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898069(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2898069
Chen LEbrahimi MTahoori M(2015)Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control PathsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5519-331:2(193-206)Online publication date: 1-Apr-2015
https://dl.acm.org/doi/10.1007/s10836-015-5519-3
Lee SSakallah K(2014)Unbounded Scalable Verification Based on Approximate Property-Directed Reachability and Datapath AbstractionProceedings of the 16th International Conference on Computer Aided Verification - Volume 855910.1007/978-3-319-08867-9_56(849-865)Online publication date: 18-Jul-2014
https://dl.acm.org/doi/10.1007/978-3-319-08867-9_56
Kelley KWachs MStevenson JRichardson SHorowitz MGroeneveld PSciuto DHassoun S(2012)Removing overhead from high-level interfacesProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228502(783-789)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228502
Een NMishchenko ABrayton RBjesse PSlobodová A(2011)Efficient implementation of property directed reachabilityProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157675(125-134)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157675
Mishchenko ABrayton RJiang JJang S(2011)Scalable don't-care-based logic optimization and resynthesisACM Transactions on Reconfigurable Technology and Systems10.1145/2068716.20687204:4(1-23)Online publication date: 28-Dec-2011
https://dl.acm.org/doi/10.1145/2068716.2068720
Savoj HBerthelot DMishchenko ABrayton RBloem RSharygina N(2010)Combinational techniques for sequential equivalence checkingProceedings of the 2010 Conference on Formal Methods in Computer-Aided Design10.5555/1998496.1998524(145-150)Online publication date: 20-Oct-2010
https://dl.acm.org/doi/10.5555/1998496.1998524
Brayton RMishchenko A(2010)ABCProceedings of the 22nd international conference on Computer Aided Verification10.1007/978-3-642-14295-6_5(24-40)Online publication date: 15-Jul-2010
https://dl.acm.org/doi/10.1007/978-3-642-14295-6_5
Mony HBaumgartner JMishchenko ABrayton RBenini LDe Micheli GAl-Hashimi BMueller W(2009)Speculative reduction-based scalable redundancy identificationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875020(1674-1679)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875020
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents