Article

Improvements to combinational equivalence checking

Authors:

Alan Mishchenko,

Satrajit Chatterjee,

Robert Brayton,

Niklas EenAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 836 - 843

https://doi.org/10.1145/1233501.1233679

Published: 05 November 2006 Publication History

Abstract

The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output (i.e. proving equivalence of the output to constant 0). This paper improves on this method by (a) using more intelligent simulation, (b) using CNF-based SAT with circuit-based decision heuristics, and (c) interleaving SAT with low-effort logic synthesis. Experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. In several cases, the new solver succeeded in solving previously unsolved problems.

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Pan HZhang RXia YWang LYang FZeng XChu Z(2024)A Semi-Tensor Product based Circuit Simulation for SAT-sweeping2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546678(1-6)Online publication date: 25-Mar-2024
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Index Terms

Improvements to combinational equivalence checking
1. Hardware

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

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Published: 05 November 2006

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https://doi.org/10.1109/TCAD.2024.3434385
Pan HZhang RXia YWang LYang FZeng XChu Z(2024)A Semi-Tensor Product based Circuit Simulation for SAT-sweeping2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546678(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546678
Hu KChu Z(2023)An efficient circuit-based SAT solver and its application in logic equivalence checkingMicroelectronics Journal10.1016/j.mejo.2023.106005142(106005)Online publication date: Dec-2023
https://doi.org/10.1016/j.mejo.2023.106005
Lee SRiener HMishchenko ABrayton RDe Micheli G(2022)A Simulation-Guided Paradigm for Logic Synthesis and VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310870441:8(2573-2586)Online publication date: Aug-2022
https://doi.org/10.1109/TCAD.2021.3108704
Zha YLi JSherwood TBerger EKozyrakis C(2021)When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAsProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3445814.3446699(123-134)Online publication date: 19-Apr-2021
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Swords S(2018)Incremental SAT Library Integration Using Abstract StobjsElectronic Proceedings in Theoretical Computer Science10.4204/EPTCS.280.4280(47-60)Online publication date: 29-Oct-2018
https://doi.org/10.4204/EPTCS.280.4
Dao ALee NChen LLin MJiang JMishchenko ABrayton R(2018)Efficient computation of ECO patch functionsProceedings of the 55th Annual Design Automation Conference10.1145/3195970.3196039(1-6)Online publication date: 24-Jun-2018
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Büscher NFranz MHolzer AVeith HKatzenbeisser S(2017)On compiling Boolean circuits optimized for secure multi-party computationFormal Methods in System Design10.1007/s10703-017-0300-051:2(308-331)Online publication date: 1-Nov-2017
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Sayed-Ahmed AGroße DSoeken MDrechsler RPiskac RTalupur M(2016)Equivalence checking using Gröbner basesProceedings of the 16th Conference on Formal Methods in Computer-Aided Design10.5555/3077629.3077659(169-176)Online publication date: 3-Oct-2016
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Goldberg EPiskac RTalupur M(2016)Equivalence checking by logic relaxationProceedings of the 16th Conference on Formal Methods in Computer-Aided Design10.5555/3077629.3077643(49-56)Online publication date: 3-Oct-2016
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