article

Energy-efficient single-clock-cycle binary comparator

Authors:

Fabio Frustaci,

Stefania Perri,

Pasquale CorsonelloAuthors Info & Claims

International Journal of Circuit Theory and Applications, Volume 40, Issue 3

Pages 237 - 246

https://doi.org/10.1002/cta.720

Published: 01 March 2012 Publication History

Abstract

A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.

References

[1]

Suzuki H, Kim CH, Roy K. Fast tag comparator using diode partitioned domino for 64-bit microprocessors. IEEE Transactions on Circuits and Systems I: Regular Papers 2007; 54(2): 322–328.

[2]

Wang CC, Wu CF, Chen SH, Kao CH. In-sawing-lane multi-level BIST for known good dies of LCD drivers. IEE Electronics Letters 1999; 35(18): 1543–1544.

[3]

Wang CC, Horng IH. Realization of bidirectional associative memory using a pseudo-parallel searching approach. Proceedings of the IEEE International Conference on Neural Networks, Perth, Australia, vol. 3, 1995; 1502–1507.

[4]

Cheng SW. Arbitrary long digit integer sorter HW/SW co-design. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Kitakyushu, Japan, 21–24 January 2003; 538–543.

Digital Library

[5]

Huang CH, Wang JS. High-performance and power-efficient CMOS comparators. IEEE Journal of Solid-state Circuits 2003; 38(2): 254–262.

[6]

Lam HM, Tsui CY. High-performance single clock cycle CMOS comparator. IEE Electronics Letters 2006; 42(2): 75–77.

[7]

Perri S, Corsonello P. Fast low-cost implementation of single-clock-cycle binary comparator. IEEE Transactions on Circuits and Systems II: Express Briefs 2008; 55(12): 1239–1243.

[8]

Brent RP, Kung HT. A regular layout for parallel adders. IEEE Transactions on Computers 1982; C-31(3): 260–264.

Digital Library

[9]

Rabaey M, Chandrakasan A, Nikolic B. Digital Integrated Circuits (2nd edn). Prentice-Hall: Englewood Cliffs, NJ, 2002.

[10]

Cheng KH, Huang CS. The novel efficient design of XOR/XNOR function for adder applications. Proceedings of Sixth IEEE International Conference on Electronics, Circuits and Systems, ICECS '99, Paphos, Cyprus, vol. 1, September 1999; 29–32.

[11]

Perri S, Corsonello P, Pezzimenti F, Kantabutra V. Fast and energy-efficient Manchester carry-bypass adders. IEE Proceedings Circuits, Devices and Systems 2004; 151(6): 497–502.

[12]

Wang CC, Wu CF, Tsai KC. 1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking. IEE Proceedings Computers and Digital Techniques 1998; 145(6): 433–436.

[13]

Lam HM, Tsui CY. A MUX-based high-performance single cycle CMOS comparator. IEE Transactions on Circuits and Systems II, Express Briefs 2007; 54(7): 591–595.

[14]

Synopsys documentation {online}. Available from: .

[15]

Stine JE, Schulte MJ. A combined two's complement and floating-point comparator. Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS, Kobe, Japan, 2005.

Cited By

Kumar APrasanna ABalkind JShriraman ATsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)METAL: Caching Multi-level Indexes in Domain-Specific ArchitecturesProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640402(715-729)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640402

Energy-efficient single-clock-cycle binary comparator

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Published In

cover image International Journal of Circuit Theory and Applications

International Journal of Circuit Theory and Applications Volume 40, Issue 3

March 2012

113 pages

ISSN:0098-9886

EISSN:1097-007X

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Publisher

John Wiley and Sons Ltd.

United Kingdom

Publication History

Published: 01 March 2012

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Cited By

Kumar APrasanna ABalkind JShriraman ATsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)METAL: Caching Multi-level Indexes in Domain-Specific ArchitecturesProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640402(715-729)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640402

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