article

Partial redundancy elimination for access expressions by speculative code motion

Authors:

Motohiro Kawahito,

Hideaki Komatsu,

Toshio NakataniAuthors Info & Claims

Software—Practice & Experience, Volume 34, Issue 11

Pages 1065 - 1090

https://doi.org/10.1002/spe.604

Published: 01 September 2004 Publication History

Abstract

We present a new memory access optimization for Java to perform aggressive code motion for speculatively optimizing memory accesses by applying partial redundancy elimination (PRE) techniques. First, to reduce as many barriers as possible and to enhance code motion, we perform alias analysis to identify all the regions in which each object reference is not aliased. Secondly, we find all the possible barriers. Finally, we perform code motions in three steps. For the first step, we apply a non-speculative PRE algorithm to move load instructions and their following instructions in the backwards direction of the control flow graph. For the second step, we apply a speculative PRE algorithm to move some of them aggressively before the conditional branches. For the third step, we apply our modified version of a non-speculative PRE algorithm to move store instructions in the forward direction of the control flow graph and to even move some of them after the merge points. We implemented our new algorithm in our production-level Java just-in-time compiler. Our experimental results show that our speculative algorithm improves the average (maximum) performance by 13.1% (90.7%) for jBYTEmark and 1.4% (4.4%) for SPECjvm98 over the fastest algorithm previously described, while it increases the average (maximum) compilation time by 0.9% (2.9%) for both benchmark suites.

References

[1]

1. Carr S, Kennedy K. Scalar replacement in the presence of conditional control flow. Software--Practice and Experience 1994; 24(1):51-77.]]

[2]

2. Cooper KD, Lu J. Register promotion in C programs. Conference on Programming Language Design and Implementation. ACM Press: New York, 1997; 308-319.]]

[3]

3. Lo R, Chow F, Kennedy R, Liu SM, Tu P. Register promotion by sparse partial redundancy elimination of loads and stores. Conference on Programming Language Design and Implementation. ACM Press: New York, 1998: 26-37.]]

[4]

4. Hosking AL, Nystrom N, Whitlock D, Cutts Q, Diwan A. Partial redundancy elimination for access path expressions. Software-Practice and Experience 2001; 31(6):577-600.]]

[5]

5. Dean J, Grove D, Chambers C. Optimization of object-oriented programs using static class hierarchy. Proceedings of the 9th European Conference on Object-Oriented Programming (ECOOP '95). Springer-Verlag: Berlin, 1995; 77-101.]]

Digital Library

[6]

6. Aigner G, Holzle U. Eliminating virtual function calls in C++ programs. Proceedings of the 10th European Conference on Object-Oriented Programming (ECOOP '96). ACM Press: New York, 1996; 142-166.]]

Digital Library

[7]

7. Ishizaki K, Kawahito M, Yasue T, Komatsu H, Nakatani T. A study of devirtualization techniques for a Java just-in-time compiler. Proceedings of the International Conference on Object-Oriented Programming, Systems, Languages, and Applications. ACM Press: New York, 2000.]]

Digital Library

[8]

8. Suganuma T, Ogasawara T, Takeuchi M, Yasue T, Kawahito M, Ishizaki K, Komatsu H, Nakatani T. Overview of the IBM Java Just-in-Time compiler. IBM Systems Journal 2000; 39(1): 175-193.]]

[9]

9. Kawahito M, Komatsu H, Nakatani T. Effective null pointer check elimination utilizing hardware trap. Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Cambridge, MA, November 2000. ACM Press: New York, 2000; 139-149.]]

Digital Library

[10]

10. Ishizaki K, Kawahito M, Takeuchi M, Ogasawara T, Suganuma T, Onodera T, Komatsu H, Nakatani T. Design, implementation, and evaluation of optimizations in a just-in-time compiler. Proceedings of the ACM SIGPLAN Java Grande Conference. ACM Press: New York, 1999.]]

[11]

11. Knoop J, Rüthing O, Steffen B. Optimal code motion: Theory and practice. ACM Transactions on Programming Languages and Systems 1994; 16(4):1117-1155.]]

[12]

12. Horspool RN, Ha HC. Partial redundancy elimination based on a cost-benefit analysis. Proceedings 8th Israeli Conference on Cnmputer Systems and Software Engineering, Herzliya, Israel, June 1997. IEEE Computer Society Press: Los Alamitos, CA, 1997; 111-118.]]

Digital Library

[13]

13. Gupta R, Berson D, Fang J. Path profile guided partial redundancy elimination using speculation. IEEE Conference on Computer Languages. IEEE Computer Society Press: Los Alamitos, CA, 1998.]]

[14]

14. Bodik R, Gupta R. Array data flow analysis for load-store optimizations in superscalar architectures. Languages and Compilers for Parallel Computing. Springer-Verlag: Berlin, 1995; 1-15.]]

[15]

15. Bodik R, Gupta R, Soffa ML. Load-reuse analysis: Design and evaluation. SIGPLAN Conference on Programming Language Design and Implementation. ACM Press: New York, 1999; 64-76.]]

[16]

16. Fink SJ, Knobe K, Sarkar V. Unified analysis of array and object references in strongly typed languages. Static Analysis Symposium. Springer-Verlag: Berlin, 2000; 155-174.]]

[17]

17. Muchnick SS. Advanced Compiler Design and Implementation. Morgan Kaufmann: San Mateo, CA, 1997.]]

[18]

18. Zahir R, Ross J, Morris D, Hess D. as and compiler considerations in the design of the ia-64 architecture. Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, November 2000. ACM Press: New York, 2000; 212-221.]]

Digital Library

[19]

19. Gosling J, Joy B, Steele G. The Java Language Specification. Addison-Wesley: Reading, MA, 1996.]]

[20]

20. Bodik R, Gupta R, Soffa ML. Complete removal of redundant expressions. SIGPLAN Conference on Programming Language Design and Implementation. ACM Press: New York, 1998; 1-14.]]

[21]

21. Gupta M, Choi JD, Hind M. Optimizing Java Programs in the Presence of Exceptions (Lectures Notes in Computer Science, vol. 1850). Springer-Verlag: Berlin, 2000; 422-446.]]

[22]

22. Pugh W. Fixing the Java memory model. Java Grande Conference. ACM Press: New York, 1999; 89-98.]]

[23]

23. Ghemawat S, Randall KH, Scales DJ. Field analysis: Getting useful and low-cost interprocedural information. Conference on Programming Language Design and Implementation. ACM Press: New York, 2000; 334-344.]]

[24]

24. Kawahito M, Komatsu H, Nakatani T. Effective sign extension elimination. Conference on Programming Language Design and Implementation (PLDI), Berlin, Germany, June 2002. ACM Press: New York, 2002; 187-198.]]

[25]

25. Bodik R, Gupta R, Sarkar V. ABCD: Eliminating array bounds checks on demand. SIGPLAN Conference on Programming Language Design and Implementation. ACM Press: New York, 2000; 321-333.]]

[26]

26. Standard Performance Evaluation Corp. Spec jvm98 benchmarks, http://www.spec.org/osg/jvm98/ {6 April 2004}]]

[27]

27. Suganuma T, Yasue T, Kawahito M, Komatsu H, Nakatani T. A dynamic optimization framework for a Java Just-In-Time compiler. Proceedings of the International Conference on Object-Oriented Programming, Systems, Languages, and Applications. ACM Press: New York, 2001.]]

Digital Library

[28]

28. Ogata K, Komatsu H, Nakatani T. Bytecode fetch optimization for Java interpreter. Conference on Architectural Support for Programming language and Operating Systems. ACM Press: New York, 2002; 58-67.]]

[29]

29. Wagner TA, Maverick V, Graham SL, Harrison MA. Accurate static estimators for program optimization. Conference on Programming Language Design and Implementation. ACM Press: New York, 1994; 85-96.]]

Cited By

Sumikawa YTakimoto M(2016)Global load instruction aggregation based on dimensions of arraysComputers and Electrical Engineering10.1016/j.compeleceng.2015.08.02050:C(180-199)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1016/j.compeleceng.2015.08.020
Kawahito MKomatsu HMoriyama TInoue HNakatani T(2013)Idiom recognition framework using topological embeddingACM Transactions on Architecture and Code Optimization10.1145/251243110:3(1-34)Online publication date: 16-Sep-2013
https://dl.acm.org/doi/10.1145/2512431
Brown RHorspool RKrall AMössenböck H(2010)Local redundant polymorphism query eliminationProceedings of the 8th International Conference on the Principles and Practice of Programming in Java10.1145/1852761.1852773(78-88)Online publication date: 15-Sep-2010
https://dl.acm.org/doi/10.1145/1852761.1852773
Show More Cited By

Index Terms

Partial redundancy elimination for access expressions by speculative code motion
1. Information systems
  1. Data management systems
    1. Data structures
      1. Data access methods
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language types
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Allocation / deallocation strategies

Recommendations

An evaluation of speculative instruction execution on simultaneous multithreaded processors

Modern superscalar processors rely heavily on speculative execution for performance. For example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for SPECINT95 are speculative. Without speculation, processor resources ...
A compiler framework for speculative optimizations

Speculative execution, such as control speculation or data speculation, is an effective way to improve program performance. Using edge/path profile information or simple heuristic rules, existing compiler frameworks can adequately incorporate and exploit ...
An SSA-based algorithm for optimal speculative code motion under an execution profile
PLDI '11

To derive maximum optimization benefits from partial redundancy elimination (PRE),it is necessary to go beyond its safety constraint. Algorithms for optimal speculative code motion have been developed based on the application of minimum cut to flow ...

Comments

Information & Contributors

Information

Published In

cover image Software—Practice & Experience

Software—Practice & Experience Volume 34, Issue 11

September 2004

93 pages

ISSN:0038-0644

Issue’s Table of Contents

Publisher

John Wiley & Sons, Inc.

United States

Publication History

Published: 01 September 2004

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Sumikawa YTakimoto M(2016)Global load instruction aggregation based on dimensions of arraysComputers and Electrical Engineering10.1016/j.compeleceng.2015.08.02050:C(180-199)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1016/j.compeleceng.2015.08.020
Kawahito MKomatsu HMoriyama TInoue HNakatani T(2013)Idiom recognition framework using topological embeddingACM Transactions on Architecture and Code Optimization10.1145/251243110:3(1-34)Online publication date: 16-Sep-2013
https://dl.acm.org/doi/10.1145/2512431
Brown RHorspool RKrall AMössenböck H(2010)Local redundant polymorphism query eliminationProceedings of the 8th International Conference on the Principles and Practice of Programming in Java10.1145/1852761.1852773(78-88)Online publication date: 15-Sep-2010
https://dl.acm.org/doi/10.1145/1852761.1852773
Murphy BMenon VSchneider FShpeisman TAdl-Tabatabai ASoffa MDuesterwald E(2008)Fault-safe code motion for type-safe languagesProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356078(144-154)Online publication date: 6-Apr-2008
https://dl.acm.org/doi/10.1145/1356058.1356078
Kawahito MKomatsu HMoriyama TInoue HNakatani T(2006)A new idiom recognition framework for exploiting hardware-assist instructionsACM SIGARCH Computer Architecture News10.1145/1168919.116890534:5(382-393)Online publication date: 20-Oct-2006
https://dl.acm.org/doi/10.1145/1168919.1168905
Kawahito MKomatsu HMoriyama TInoue HNakatani T(2006)A new idiom recognition framework for exploiting hardware-assist instructionsACM SIGPLAN Notices10.1145/1168918.116890541:11(382-393)Online publication date: 20-Oct-2006
https://dl.acm.org/doi/10.1145/1168918.1168905
Kawahito MKomatsu HMoriyama TInoue HNakatani T(2006)A new idiom recognition framework for exploiting hardware-assist instructionsACM SIGOPS Operating Systems Review10.1145/1168917.116890540:5(382-393)Online publication date: 20-Oct-2006
https://dl.acm.org/doi/10.1145/1168917.1168905
Kawahito MKomatsu HMoriyama TInoue HNakatani TShen JMartonosi M(2006)A new idiom recognition framework for exploiting hardware-assist instructionsProceedings of the 12th international conference on Architectural support for programming languages and operating systems10.1145/1168857.1168905(382-393)Online publication date: 23-Oct-2006
https://dl.acm.org/doi/10.1145/1168857.1168905
Kawahito MKomatsu HNakatani TDing CBlackburn S(2004)Instruction combining for coalescing memory accesses using global code motionProceedings of the 2004 workshop on Memory system performance10.1145/1065895.1065897(2-11)Online publication date: 8-Jun-2004
https://dl.acm.org/doi/10.1145/1065895.1065897

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents