Bus power estimation and power-efficient bus arbitration for system-on-a-chip embedded systems

In a system-on-a-chip embedded system, an external bus connects embedded processor cores, I/O peripherals, direct memory access (DMA) and off-chip memory. The power on the external bus makes up a significant portion of the overall power use in the system. In this paper, we will focus on the address and control bus power on the external bus. We have developed an external bus power model which monitors memory bus state transitions and models power-efficient bus arbitration schemes power. Our model allows us to consider performance/power trade-offs in managing off-chip memory accesses. We use an Analog Devices ADSP-BF533 multimedia system-on-a-chip embedded system as our target architecture to validate our model. By using more power-efficient external bus arbitration schemes, we find we can reduce overall power by as much as 18%.