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Register allocation for programs in SSA-Form

Published: 30 March 2006 Publication History

Abstract

As register allocation is one of the most important phases in optimizing compilers, much work has been done to improve its quality and speed. We present a novel register allocation architecture for programs in SSA-form which simplifies register allocation significantly. We investigate certain properties of SSA-programs and their interference graphs, showing that they belong to the class of chordal graphs. This leads to a quadratic-time optimal coloring algorithm and allows for decoupling the tasks of coloring, spilling and coalescing completely. After presenting heuristic methods for spilling and coalescing, we compare our coalescing heuristic to an optimal method based on integer linear programming.

References

[1]
Chaitin, G.J., Auslander, M.A., Chandra, A.K., Cocke, J., Hopkins, M.E., Markstein, P.W.: Register allocation via graph coloring. Journal of Computer Languages 6 (1981) 45-57
[2]
Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocation. ACM Trans. Program. Lang. Syst. 16 (1994) 428-455
[3]
Golumbic, M.C.: Algorithmic Graph Theory And Perfect Graphs. Academic Press (1980)
[4]
Budimlić, Z., Cooper, K.D., Harvey, T.J., Kennedy, K., Oberg, T.S., Reeves, S.W.: Fast copy coalescing and live-range identification. In: Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation, ACM Press (2002) 25-32
[5]
Bouchez, F.: Allocation de registres et vidage en mémoire. Master's thesis, ÉNS Lyon (2005)
[6]
Diestel, R.: Graph Theory. 3 edn. Volume 173 of Graduate Texts in Mathematics. Springer (2005)
[7]
Bergner, P., Dahl, P., Engebretsen, D., O'Keefe, M.: Spill code minimization via interference region spilling. In: PLDI '97: Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, New York, NY, USA, ACM Press (1997) 287-295
[8]
Chow, F.C., Hennessy, J.L.: The priority-based coloring approach to register allocation. ACM Trans. Program. Lang. Syst. 12 (1990) 501-536
[9]
Hsu, W.C., Fisher, C.N., Goodman, J.R.: On the Minimization of Loads/Stores in Local Register Allocation. IEEE Trans. Softw. Eng. 15 (1989) 1252-1260
[10]
Guo, J., Garzaran, M.J., Padua, D.: The Power of Belady's Algorithm in Register Allocation for Long Basic Blocks. The 16th International Workshop on Languages and Compilers for Parallel Computing (2003)
[11]
Belady, L.: A Study of Replacement of Algorithms for a Virtual Storage Computer. IBM Systems Journal 5 (1966) 78-101
[12]
Cytron, R., Ferrante, J., Rosen, B.K., Wegman, M.N., Zadek, F.K.: Efficiently computing static single assignment form and the control dependence graph. ACM Transactions on Programming Languages and Systems 13 (1991) 451-490
[13]
Briggs, P., D.Cooper, K., Harvey, T.J., Simpson, L.T.: Practical Improvements to the Construction and Destruction of Static Single Assignment Form. Software: Practice and Experience 28 (1998) 859-881
[14]
Hack, S., Grund, D., Goos, G.: Towards Register Allocation for Programs in SSAform. Technical Report 2005-27, Universität Karlsruhe (2005)
[15]
Lindenmaier, G., Beck, M., Boesler, B., Geiß, R.: Firm, an intermediate language for compiler research. Technical Report 2005-8, University of Karlsruhe (2005)
[16]
George, L., Appel, A.W.: Iterated register coalescing. ACM Trans. Program. Lang. Syst. 18 (1996) 300-324
[17]
Park, J., Moon, S.M.: Optimistic register coalescing. ACM Trans. Program. Lang. Syst. 26 (2004) 735-765
[18]
Andersson, C.: Register Allocation By Optimal Graph Coloring. In Hedin, G., ed.: CC 2003. Volume 2622 of LNCS., Heidelberg, Springer-Verlag (2003) 33-45
[19]
Pereira, F.M.Q., Palsberg, J.: Register allocation via coloring of chordal graphs. In: Proceedings of APLAS'05. (2005)
[20]
Hack, S.: Interference Graphs of Programs in SSA-form. Technical Report 2005-15, Universität Karlsruhe (2005)
[21]
Brisk, P., Dabiri, F., Macbeth, J., Sarrafzadeh, M.: Polynomial time graph coloring register allocation. In: 14th International Workshop on Logic and Synthesis, ACM Press (2005)

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Published In

cover image Guide Proceedings
CC'06: Proceedings of the 15th international conference on Compiler Construction
March 2006
276 pages
ISBN:354033050X
  • Editors:
  • Alan Mycroft,
  • Andreas Zeller

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Springer-Verlag

Berlin, Heidelberg

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Published: 30 March 2006

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  • (2023)RL4ReAl: Reinforcement Learning for Register AllocationProceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction10.1145/3578360.3580273(133-144)Online publication date: 17-Feb-2023
  • (2023)A Sound and Complete Algorithm for Code Generation in Distance-Based ISAProceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction10.1145/3578360.3580263(73-84)Online publication date: 17-Feb-2023
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