Energy Reduction Method by Compiler Optimization
Abstract
References
Index Terms
- Energy Reduction Method by Compiler Optimization
Recommendations
Energy-efficient register caching with compiler assistance
The register file is a critical component in a modern superscalar processor. It must be large enough to accommodate the results of all in-flight instructions. It must also have enough ports to allow simultaneous issue and writeback of many values each ...
A Front-end Execution Architecture for High Energy Efficiency
MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on MicroarchitectureSmart phones and tablets have recently become widespread and dominant in the computer market. Users require that these mobile devices provide a high-quality experience and an even higher performance. Hence, major developers adopt out-of-order ...
An ultra-energy-efficient crosstalk-immune interconnect architecture based on multilayer graphene nanoribbons for deep-nanometer technologies
AbstractAn ultra-energy-efficient interconnect structure based on multilayer graphene nanoribbon (MLGNR) interconnects for deep-nanometer technologies is proposed herein. First, a low-swing interconnect based on MLGNRs and high-performance interface ...
Comments
Information & Contributors
Information
Published In
- Editors:
- Xingming Sun,
- Xiaorui Zhang,
- Zhihua Xia,
- Elisa Bertino
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
View options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in