Article

Getting Formal Verification into Design Flow

Authors:

Michael KatelmanAuthors Info & Claims

FM '08: Proceedings of the 15th international symposium on Formal Methods

Pages 12 - 32

https://doi.org/10.1007/978-3-540-68237-0_2

Published: 26 May 2008 Publication History

Abstract

The ultimate goal of formal methods is to provide assurances about the quality, performance, security, etc. of systems. While formal tools have advanced greatly over the past two decades, widespread proliferation has not yet occurred, and the full impact of formal methods is still to be realized. This paper presents some ideas on how to catalyze the growth of formal techniques in day-to-day engineering practice. We draw on our experience as hardware engineers that want to use, and have tried to use, formal methods in our own designs. The points we make have probably been made before. However we illustrate each one with concrete designs. Our examples support three major themes: (1) correctness depends highly on the application and even a collection of formal methods cannot handle the whole problem; (2) high-level design languages can facilitate the interaction between design and formal methods; and (3) formal method tools should be presented as integrated debugging aids as opposed to one requiring mastering a foreign language or esoteric concepts.

References

[1]

Paulson, L.C.: The Relative Consistency of the Axiom of Choice Mechanized using Isabelle/ZF. London Mathematical Society Journal of Computation and Mathematics 6 (2003).

[2]

McMillan, K.L.: Symbolic Model Checking: An Approach to the State Explosion Problem. PhD thesis, Carnegie Mellon University (1992).

[3]

Bryant, R.E., Lahiri, S.K., Seshia, S.A.: Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In: 14th International Conference on Computer Aided Verification (CAV), Copenhagen, Denmark (2002).

[4]

de Moura, L., Bjorner, N.: Z3: An Efficient SMT Solver. In: 14th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Budapest, Hungary (2008).

[5]

Manolios, P., Srinivasan, S.K., Vroon, D.: BAT: The Bit-Level Analysis Tool. In: Proceedings of the 19th International Conference on Computer Aided Verification (CAV), Berlin, Germany (2007).

[6]

Moskewicz, M.W., Madigan, C.F., Zhao, Y., Zhang, L., Malik, S.: Chaff: engineering an efficient SAT solver. In: Proceedings of the 38th conference on Design automation (DAC), Las Vegas, NV (2001).

[7]

Mentor Graphics Corp.: 0-In® Formal Verification, www.mentor.com/products/fv/abv/0-in_fv/

[8]

Synopsys, Inc.: Formality® Equivalence Checker, www.synopsys.com/products/verification/

[9]

Mentor Graphics Corp.: FormalPro™, www.mentor.com/products/fv/ev/formalpro/

[10]

Cadence Design Systems, Inc.: Cadence® Encounter® Conformal® Equivalence Checker, www.cadence.com/products/digital_ic/conformal/index.aspx

[11]

Jasper Design Automation, Inc.: JasperGold® Verification System, www.jasper-da.com/products_jaspergold.htm

[12]

Cadence Design Systems, Inc.: Incisive® Formal Verifier, www.cadence.com/ products/functional_ver/incisive_formal_verifier/index.aspx

[13]

Meadows, C.: The NRL Protocol Analyzer: An Overview. The Journal of Logic Programming 26(2), 113-131 (1996).

[14]

Kwiatkowska, M.Z., Norman, G., Sproston, J.: Probabilistic Model Checking of the IEEE 802.11 Wireless Local Area Network Protocol. In: Proceedings of the Second Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification (PAPM-PROBMIV), Copenhagen, Denmark (2002).

[15]

Burch, J.R., Dill, D.L.: Automatic Verification of Pipelined Microprocessor Control. In: Proceedings of the 6th International Conference on Computer Aided Verification (CAV), Stanford, CA (1994).

[16]

Stoy, J.E., Shen, X., Arvind.: Proofs of Correctness of Cache-Coherence Protocols. In: Oliveira, J.N., Zave, P. (eds.) FME 2001. LNCS, vol. 2021, pp. 47-71. Springer, Heidelberg (2001).

[17]

Flanagan, C., Leino, K.R.M., Lillibridge, M., Nelson, G., Saxe, J.B., Stata, R.: Extended static checking for Java. In: Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation (PLDI), San Diego, CA (2002).

[18]

Ball, T., Rajamani, S.K.: The SLAM project: debugging system software via static analysis. In: Proceedings of the 29th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL), Portland, OR (2002).

[19]

Russinoff, D.M.: A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon ^TM Processor. In: Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design (FMCAD), Austin, TX (2000).

[20]

Seger, C.J., Jones, R., O'Leary, J., Melham, T., Aagaard, M., Barrett, C., Syme, D.: An Industrially Effective Environment for Formal Hardware Verification. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 24(9), 1381-1405 (2005).

[21]

Cousot, P., Cousot, R., Feret, J., Mauborgne, L., Miné, A., Monniaux, D., Rival, X.: The ASTREÉ Analyzer. In: Proceedings of the 14th European Symposium on Programming (ESOP), Edinburgh, UK (2005).

[22]

Berry, G.: The Foundations of Esterel, 425-454 (2000).

[23]

Arvind, N.R.S., Rosenband, D.L., Dave, N.: High-level synthesis: an essential ingredient for designing complex ASICs. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA (2004).

[24]

IEEE: IEEE standard 802.11a supplement. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications (1999).

[25]

International Telecommunication Union: H.264, www.itu.int/rec/T-REC-H.264

[26]

Joshi, R., Lamport, L., Matthews, J., Tasiran, S., Tuttle, M., Yu, Y.: Checking Cache-Coherence Protocols with TLA+. Form. Methods Syst. Des. 22(2) (2003).

[27]

Arvind, S.X.: Using Term Rewriting Systems to Design and Verify Processors. IEEE Micro 19(3), 36-46 (1999).

[28]

Krstic, S., Jones, R.B., O'Leary, J.: Mothers of Pipelines. Electron. Notes Theor. Comput. Sci. 174(8), 7-22 (2007).

[29]

Manolios, P.: Correctness of Pipelined Machines. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 161-178. Springer, Heidelberg (2000).

[30]

Dave, N., Pellauer, M., Gerding, S., Arvind.: 802.11a Transmitter: A Case Study in Microarchitectural Exploration. In: Proceedings of Formal Methods and Models for Codesign (MEMOCODE), Napa, CA (2006).

[31]

Bluespec, Inc. Waltham, MA: Bluespec SystemVerilog Ver. 3.8 Reference Guide (November 2004).

[32]

Chandy, K.M., Misra, J.: Parallel Program Design: A Foundation. Addison-Wesley, Reading (1988).

[33]

Berry, G.: The Esterel v5 Language Primer Version v5P_91 (2000).

[34]

Dijkstra, E.W.: A Discipline of Programming. Prentice Hall PTR, Upper Saddle River (1997).

[35]

Dave, N., Ng, M.C., Arvind.: Automatic Synthesis of Cache-Coherence Protocol Processors Using Bluespec. In: Proc. of Formal Methods and Models for Codesign, Verona, Italy (2005).

[36]

Dave, N., Ng, M.C., Arvind.: Standard for System Verilog: Unified Hardware Design, Specification and Verification Language (IEEE Std. 1800-2007).

[37]

Holzmann, G.J.: The SPIN MODEL CHECKER: Primer and Reference Manual. Addison-Wesley, Reading (2003).

[38]

Kaufmann, M., Moore, J.S., Manolios, P.: Computer-Aided Reasoning: An Approach. Kluwer Academic Publishers, Norwell (2000).

[39]

Owre, S., Rushby, J.M., Rushby, J.M., Shankar, N.: PVS: A Prototype Verification System. In: Proceedings of the 11th International Conference on Automated Deduction (CADE), Saratoga Springs, NY (1992).

[40]

Nipkow, T., Paulson, L.C., Wenzel, M.: Isabelle/HOL: A Proof Assistant for Higher-Order Logic. Springer-Verlag, London (2002).

[41]

SRI International: Yices, yices.csl.sri.com/index.shtml

[42]

Jackson, D.: Alloy: A Lightweight Object Modelling Notation. ACM Trans. Softw. Eng. Methodol. 11(2), 256-290 (2002).

[43]

Abrial, J.-R.: The B-Book: Assigning Programs to Meanings. Cambridge University Press, New York (1996).

[44]

Lynch, N.A., Tuttle, M.R.: Hierarchical correctness proofs for distributed algorithms. In: Proceedings of the Sixth Annual ACM Symposium on Principles of Distributed Computing (PODC), Vancouver, British Columbia (1987).

[45]

Archer, L.M.H.L., Mitra, N., Umeno, S.: Specifying and Proving Properties of Timed I/O Automata in the TIOA Toolkit. In: Proceedings. Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), Napa, CA (2006).

[46]

Shen, X.: Design and Verification of Adaptive Cache Coherence Protocols. PhD thesis, MIT, Cambridge, MA (2000).

[47]

Shen, X., Rudolph, L., Arvind,: CACHET: An Adaptive Cache Coherence Protocol for Distributed Shared-Memory Systems. In: Proceedings of the 13th ACM SIGARCH International Conference on Supercomputing, IEEE Computer Society, Los Alamitos (1999).

Cited By

Matthews OSorin DHunter HMoreno JEmer JSanchez D(2017)Architecting hierarchical coherence protocols for push-button parametric verificationProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123971(477-489)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123971
Dave NKatelman MKing MMeseguer J(2011)Verification of microarchitectural refinements in rule-based systemsProceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2011.5970511(61-71)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.1109/MEMCOD.2011.5970511
Zhang MLebeck ASorin D(2010)Fractal CoherenceProceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2010.11(471-482)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1109/MICRO.2010.11
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cover image Guide Proceedings

FM '08: Proceedings of the 15th international symposium on Formal Methods

May 2008

434 pages

ISBN:9783540682356

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 26 May 2008

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Cited By

Matthews OSorin DHunter HMoreno JEmer JSanchez D(2017)Architecting hierarchical coherence protocols for push-button parametric verificationProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123971(477-489)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123971
Dave NKatelman MKing MMeseguer J(2011)Verification of microarchitectural refinements in rule-based systemsProceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2011.5970511(61-71)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.1109/MEMCOD.2011.5970511
Zhang MLebeck ASorin D(2010)Fractal CoherenceProceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2010.11(471-482)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1109/MICRO.2010.11
Woodcock JLarsen PBicarregui JFitzgerald J(2009)Formal methodsACM Computing Surveys10.1145/1592434.159243641:4(1-36)Online publication date: 9-Oct-2009
https://dl.acm.org/doi/10.1145/1592434.1592436

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