Article

Generation of control and data flow graphs from scheduled and pipelined assembly code

Authors:

David C. Zaretsky,

Prith BanerjeeAuthors Info & Claims

LCPC'05: Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing

Pages 76 - 90

https://doi.org/10.1007/978-3-540-69330-7_6

Published: 20 October 2005 Publication History

Abstract

High-level synthesis tools generally convert abstract designs described in a high-level language into a control and data flow graph (CDFG), which is then optimized and mapped to hardware. However, there has been little work on generating CDFGs from highly pipelined software binaries, which complicate the problem of determining data flow propagation and dependencies. This paper presents a methodology for generating CDFGs from highly pipelined and scheduled assembly code that correctly represents the data dependencies and propagation of data through the program control flow. This process consists of three stages: generating a control flow graph, linearizing the assembly code, and generating the data flow graph. The proposed methodology was implemented in the FREEDOM compiler and tested on 8 highly pipelined software binaries. Results indicate that data dependencies were correctly identified in the designs, allowing the compiler to perform complex optimizations to reduce clock cycles.

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Cited By

Mittal GZaretsky DTang XBanerjee P(2019)An overview of a compiler for mapping software binaries to hardwareIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90409515:11(1177-1190)Online publication date: 14-Nov-2019
https://dl.acm.org/doi/10.1109/TVLSI.2007.904095
Clemente JBeretta IRana VAtienza DSciuto D(2014)A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable PlatformsACM Transactions on Reconfigurable Technology and Systems10.1145/26115627:2(1-27)Online publication date: 4-Jul-2014
https://dl.acm.org/doi/10.1145/2611562

Index Terms

Generation of control and data flow graphs from scheduled and pipelined assembly code
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

Index terms have been assigned to the content through auto-classification.

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Information & Contributors

Information

Published In

cover image Guide Proceedings

LCPC'05: Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing

October 2005

476 pages

ISBN:3540693297

Editors:
Eduard Ayguadé
BSC-UPC
,
Gerald Baumgartner
Department of Computer Science, Louisiana State University, Baton Rouge, LA
,
J. Ramanujam
Dept. of Electrical and Computer Engg., Louisiana State University, Baton Rouge, LA
,
P. Sadayappan
Department of Computer Science and Engineering, The Ohio State University, 2015 Neil Avenue, Columbus, OH

Sponsors

NSF: National Science Foundation
International Business Machines Corporation: International Business Machines Corporation

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 20 October 2005

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Cited By

Mittal GZaretsky DTang XBanerjee P(2019)An overview of a compiler for mapping software binaries to hardwareIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90409515:11(1177-1190)Online publication date: 14-Nov-2019
https://dl.acm.org/doi/10.1109/TVLSI.2007.904095
Clemente JBeretta IRana VAtienza DSciuto D(2014)A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable PlatformsACM Transactions on Reconfigurable Technology and Systems10.1145/26115627:2(1-27)Online publication date: 4-Jul-2014
https://dl.acm.org/doi/10.1145/2611562

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