Article

Exponent monte carlo for quick statistical circuit simulation

Authors:

Vladimir Matvejev,

Philippe Roussel,

Petr Dobrovolný,

Miguel MirandaAuthors Info & Claims

PATMOS'09: Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Pages 36 - 45

https://doi.org/10.1007/978-3-642-11802-9_8

Published: 09 September 2009 Publication History

Abstract

The main goals of this article are to report an implementation and a quantitative study of Exponent Monte Carlo, an enhanced version of Monte Carlo for verifying high circuit yield in the presence of random process variations. Results on industry-grade standard cell netlists and compact models in 45nm show that EMC predicts reasonable results at least 1,000 times faster than MC.

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Centurelli, F., Giancane, L., Olivieri, M., Scotti, G., Trifiletti, A.: A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. In: Azémard, N., Svensson, L. (eds.) PATMOS 2007. LNCS, vol. 4644, pp. 516-525. Springer, Heidelberg (2007).

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Matvejev, V.: Optimal Gamma in Exponent Monte Carlo Simulation of SRAM. Master's thesis, Univ. Furtwangen (2009).

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Cited By

Antoniadis CKarakonstantis GEvmorfopoulos NBurg AStamoulis GNebel WAtienza D(2015)On the statistical memory architecture exploration and optimizationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755876(543-548)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755876

Index Terms

Exponent monte carlo for quick statistical circuit simulation
1. Mathematics of computing
  1. Probability and statistics
    1. Probabilistic reasoning algorithms
      1. Markov-chain Monte Carlo methods

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Published In

cover image Guide Proceedings

PATMOS'09: Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

September 2009

368 pages

ISBN:3642118011

Editors:
José Monteiro
INESC-ID / IST, TU Lisbon, Lisbon, Portugal
,
René Leuken
EEMCS/MECE/CAS, Delft University of Technology, Mekelweg 4, H17 CAS, Delft, CD, The Netherlands

Sponsors

NIRICT Design Lab: NIRICT Design Lab
IEEE
Cadence Design Systems

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 09 September 2009

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Cited By

Antoniadis CKarakonstantis GEvmorfopoulos NBurg AStamoulis GNebel WAtienza D(2015)On the statistical memory architecture exploration and optimizationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755876(543-548)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755876

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