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Instruction-level parallel processing: history, overview, and perspective

Authors:

B. Ramakrishna Rau and

Joseph A. FisherAuthors Info & Claims

The Journal of Supercomputing, Volume 7, Issue 1-2

Pages 9 - 50

https://doi.org/10.1007/BF01205181

Published: 01 May 1993 Publication History

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Raskar SMonsalve Diaz JApplencourt TKumaran KGao GVieira MCardellini VDi Marco ATuma P(2023)Implementation of Dataflow Software Pipelining for Codelet ModelProceedings of the 2023 ACM/SPEC International Conference on Performance Engineering10.1145/3578244.3583734(161-172)Online publication date: 15-Apr-2023
https://dl.acm.org/doi/10.1145/3578244.3583734
Tsmots IRabyk VKryvinska NYatsymirskyy MTeslyuk V(2022)Design of the Processors for Fast Cosine and Sine Fourier TransformsCircuits, Systems, and Signal Processing10.1007/s00034-022-02012-841:9(4928-4951)Online publication date: 1-Sep-2022
https://dl.acm.org/doi/10.1007/s00034-022-02012-8
Lozano RCarlsson MBlindell GSchulte C(2019)Combinatorial Register Allocation and Instruction SchedulingACM Transactions on Programming Languages and Systems10.1145/333237341:3(1-53)Online publication date: 2-Jul-2019
https://dl.acm.org/doi/10.1145/3332373
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cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 7, Issue 1-2

Special issue on instruction-level parallelism

May 1993

262 pages

ISSN:0920-8542

Editors:
Richard Draper
Supercomputing Research Center
,
John Riganati
Supercomputing Research Center

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Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 May 1993

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Raskar SMonsalve Diaz JApplencourt TKumaran KGao GVieira MCardellini VDi Marco ATuma P(2023)Implementation of Dataflow Software Pipelining for Codelet ModelProceedings of the 2023 ACM/SPEC International Conference on Performance Engineering10.1145/3578244.3583734(161-172)Online publication date: 15-Apr-2023
https://dl.acm.org/doi/10.1145/3578244.3583734
Tsmots IRabyk VKryvinska NYatsymirskyy MTeslyuk V(2022)Design of the Processors for Fast Cosine and Sine Fourier TransformsCircuits, Systems, and Signal Processing10.1007/s00034-022-02012-841:9(4928-4951)Online publication date: 1-Sep-2022
https://dl.acm.org/doi/10.1007/s00034-022-02012-8
Lozano RCarlsson MBlindell GSchulte C(2019)Combinatorial Register Allocation and Instruction SchedulingACM Transactions on Programming Languages and Systems10.1145/333237341:3(1-53)Online publication date: 2-Jul-2019
https://dl.acm.org/doi/10.1145/3332373
Leet CChen SGao KYang Y(2019)PrecedenceProceedings of the 2019 ACM Symposium on SDN Research10.1145/3314148.3314348(1-7)Online publication date: 3-Apr-2019
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Nongpoh BRay RDas MBanerjee A(2019)Enhancing Speculative Execution With Selective Approximate ComputingACM Transactions on Design Automation of Electronic Systems10.1145/330765124:2(1-29)Online publication date: 14-Feb-2019
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Lozano RSchulte C(2019)Survey on Combinatorial Register Allocation and Instruction SchedulingACM Computing Surveys10.1145/320092052:3(1-50)Online publication date: 18-Jun-2019
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Zhou BHuang YXu JGuo SQi H(2019)Memory latency optimizations for the elementary functions on the Sunway architectureThe Journal of Supercomputing10.1007/s11227-018-02741-175:7(3917-3944)Online publication date: 1-Jul-2019
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Lei YChen Y(2018)Optimization of Specific Instruction Set Processor for Image AlgorithmsProcedia Computer Science10.1016/j.procs.2018.04.202131:C(182-191)Online publication date: 1-May-2018
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Bhagyanath ASchneider KTalpin J(2016)Optimal compilation for exposed datapath architectures with buffered processing units by SAT solversProceedings of the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343414.3343435(143-152)Online publication date: 18-Nov-2016
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Lee JLee JLee JPaek Y(2014)Improving performance of loops on DIAM-based VLIW architecturesACM SIGPLAN Notices10.1145/2666357.259782549:5(135-144)Online publication date: 12-Jun-2014
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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

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Instruction-level parallelism

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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

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