research-article

Area-time lower-bound techniques with applications to sorting

Authors:

F. P. PreparataAuthors Info & Claims

Algorithmica, Volume 1, Issue 1-4

Pages 65 - 91

https://doi.org/10.1007/BF01840437

Published: 01 January 1986 Publication History

Abstract

Thearea-time complexity of VLSI computations is constrained by the flow and the storage of information in the two-dimensional chip. We study here the information exchanged across the boundary of the cells of asquare-tessellation of the layout. When the information exchange is due to thefunctional dependence between variables respectively input and output on opposite sides of a cell boundary, lower bounds are obtained on theAT² measure (which subsume bisection bounds as a special case). When information exchange is due to thestorage saturation of the tessellation cells, a new type of lower bound is obtained on theAT measure.

In the above arguments, information is essentially viewed as a fluid whose flow is uniquely constrained by the available bandwidth. However, in some computations, the flow is kept below capacity by the necessity to transform information before an output is produced. We call this mechanismcomputational friction and show that it implies lower bounds on theAT/logA measure.

Regimes corresponding to each of the three mechanisms described above can appear by varying the problem parameters, as we shall illustrate by analyzing the problem of sortingn keys each ofk bits, for whichAT²,AT, andAT/logA bounds are derived. Each bound is interesting, since it dominates the other two in a suitable range of key lengths and computations times.

References

[1]

C. D. Thompson,A Complexity Theory for VLSI, Ph.D. Thesis, Dept. of Comp. Science, Carnegie-Mellon University; August 1980.

[2]

Johnson R. B. The complexity of a VLSI adder Information Processing Letters 1980 11 n. 2 92-93

[3]

Baudet G. M. Kung H. T., Sproull R., and Steele G. On the area required by VLSI circuits VLSI Systems and Computations 1981 Rockville, MD Computer Science Press 100-107

[4]

Z. Kedem, “Optimal allocation of computational resources in VLSI,”Proc. 23rd Annual Symposium on the Foundations of Computer Science, Chicago, IL, pp. 379–386; November 1982.

[5]

El Gamal A., Greene J. W., and Pang K. F. VLSI complexity of coding Proceedings 1984 Conference on Advanced Research in VLSI 1984 Cambridge, MA M.I.T.

[6]

D. Angluin, “VLSI; On the merits of batching,”manuscript; April 1982.

[7]

A. Siegel, “Minimal storage sorting circuits,”IEEE Trans, on Comput., vol. C-34, n. 4; April 1985.

[8]

S. E. Hambrush and J. Simon, “Solving undirected graph problems on VLSI,”CS-81-23,Computer Science Department, Pennsylvania State Univ., Univ. Park, PA, December 1981.

[9]

Ja'Ja' J. The VLSI complexity of selected graph problems Journal of the ACM 1984 31 No. 2 377-391

[10]

A. C. C. Yao, “Some complexity questions related to distributive computing,”Proc. 11th Annual ACM Symposium on Theory of Computing, Atlanta, GA, pp. 209–213; April 1979.

[11]

A. C. C. Yao, “The entropie limitations on VLSI computations,”Proc. 13th Annual ACM Symposium on Theory of Computing, Milwaukee, WI, pp. 308–311; April 1981.

[12]

Ja'Ja' J. and Kumar V. K. P. “Information transfer in distributed computing with applications to VLSI Journal of the ACM 1984 31 n. 1 150-162

[13]

Savage J. E. Area-time tradeoffs for matrix multiplication and related problems in VLSI models Journal of Computer System Science 1981 22 n. 2 230-242

[14]

Brent R. P. and Kung H. T. The chip complexity of binary arithmetic Journal of the ACM 1981 28 n. 3 521-534

[15]

F. T. Leighton, “Tight bounds on the complexity of parallel sorting,”Proc. 16th Annual ACM Symposium on Theory of Computing, Washington, D.C., pp. 71–80; April 1984. (AlsoIEEE Trans. on Comput.; April 1985.)

[16]

P. Duris, O. Sykora, C. Thompson, and I. Vrto, “A tight chip area lower bound for sorting,”Computers and Artificial Intelligence, to appear; 1985.

[17]

Ullman J. D. Computational Aspects of VLSI 1983 Rockville, MD Computer Science Press

[18]

C. D. Thompson and D. Angluin, “OnAT² lower bounds for sorting,”manuscript draff; March 1983.

[19]

A. Siegel, “Tight area bounds and provably goodAT² bounds for sorting circuits,” Tech. Report #122 Courant Institute, New York University; June 1984.

[20]

G. Bilardi,The Area-Time Complexity of Sorting, Ph.D. Thesis, Univ. of Illinois; December 1984.

[21]

Bilardi G. and Preparata F. P. An architecture for bitonic sorting with optimal VLSI performance IEEE Trans. Comp. 1984 C-33 n. 7 640-651

[22]

G. Bilardi and F. P. Preparata, “A minimum area VLSI network forO(logN) time sorting,”Proc. 16th Annual ACM Symposium on Theory of Computing, Washington, D.C., pp. 64–70; April 1984. (AlsoIEEE Trans. on Comput., April 1985.)

[23]

Bilardi G. and Preparata F. P. The VLSI optimality of the AKS sorting network Information Processing Letters 1985 20 n. 2 55-59

[24]

Bilardi G. and Preparata F. P. The influence of key length on the area-time complexity of sorting 1985 Nauplion, Greece I. C. A. L. P.

[25]

R. Cole and A. Siegel, “Optimal VLSI circuits for sorting,” manuscript; 1985.

[26]

Thompson C. D. The VLSI complexity of sorting IEEE Trans. Comp. 1983 C-32 n. 12 1171-1184

Cited By

Bilardi GScquizzato MSilvestri F(2018)A Lower Bound Technique for Communication in BSPACM Transactions on Parallel Computing10.1145/31817764:3(1-27)Online publication date: 20-Feb-2018
https://dl.acm.org/doi/10.1145/3181776
Ballard GDemmel JGearhart ALipshitz BOltchik YSchwartz OToledo S(2016)Network topologies and inevitable contentionProceedings of the First Workshop on Optimization of Communication in HPC10.5555/3018058.3018063(39-52)Online publication date: 13-Nov-2016
https://dl.acm.org/doi/10.5555/3018058.3018063
Bilardi GFantozzi C(2011)New area-time lower bounds for the multidimensional DFTProceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 11910.5555/2483191.2483205(111-120)Online publication date: 17-Jan-2011
https://dl.acm.org/doi/10.5555/2483191.2483205
Show More Cited By

Index Terms

Area-time lower-bound techniques with applications to sorting

Index terms have been assigned to the content through auto-classification.

Recommendations

Minimum Storage Sorting Networks

This paper analyzes how to sort n k-bit numbers in a minimum storage network. The techniques also give new AT ² lower bounds for a VLSI sorting model. The principal results in this paper are as follows. Lower bounds are given for the minimum storage (...
A simplified derivation of timing complexity lower bounds for sorting by comparisons

We present a simplified derivation of the fact that the complexity-theoretic lower bound of comparison-based sorting algorithms, both for the worst-case and for the average-case time measure, is Ω(nlogn).

The standard proofs typically are directly ...
A lower bound on the average-case complexity of shellsort

We demonstrate an Ω(pn^1+1/p) lower bound on the average-case running time (uniform distribution) of p-pass Shellsort. This is the first nontrivial general lower bound for average-case Shellsort.

Reviews

Reviewer: Abraham Kandel

.abstract The area-time complexity of VLSI computations is constrained by the flow and the storage of information in the two-dimensional chip. We study here the information exchanged across the boundary of the cells of a square-tessellation of the layout. When the information exchange is due to the functional dependence between variables, respectively, input and output on opposite sides of a cell boundary, lower bounds are obtained on the AT 2 measure (which subsume bisection bounds as a special case). When information exchange is due to the storage saturation of the tessellation cells, a new type of lower bound is obtained on the AT measure. — From the Authors' Abstract The bounds derived in this interesting paper are quite useful and should interest researchers in the area of principal measures of performance of VLSI circuits.

Access critical reviews of Computing literature here

Become a reviewer for Computing Reviews.

Comments

Information & Contributors

Information

Published In

cover image Algorithmica

Algorithmica Volume 1, Issue 1-4

Nov 1986

517 pages

ISSN:0178-4617

Issue’s Table of Contents

© Springer-Verlag New York Inc. 1986.

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 January 1986

Revision received: 27 September 1985

Received: 29 April 1985

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Bilardi GScquizzato MSilvestri F(2018)A Lower Bound Technique for Communication in BSPACM Transactions on Parallel Computing10.1145/31817764:3(1-27)Online publication date: 20-Feb-2018
https://dl.acm.org/doi/10.1145/3181776
Ballard GDemmel JGearhart ALipshitz BOltchik YSchwartz OToledo S(2016)Network topologies and inevitable contentionProceedings of the First Workshop on Optimization of Communication in HPC10.5555/3018058.3018063(39-52)Online publication date: 13-Nov-2016
https://dl.acm.org/doi/10.5555/3018058.3018063
Bilardi GFantozzi C(2011)New area-time lower bounds for the multidimensional DFTProceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 11910.5555/2483191.2483205(111-120)Online publication date: 17-Jan-2011
https://dl.acm.org/doi/10.5555/2483191.2483205
Bilardi GFantozzi C(2011)New area-time lower bounds for the multidimensional DFTProceedings of the Seventeenth Computing: The Australasian Theory Symposium - Volume 11910.5555/2461196.2461210(111-120)Online publication date: 17-Jan-2011
https://dl.acm.org/doi/10.5555/2461196.2461210
Bilardi GPietracaprina APucci GSchifano FTripiccione R(2005)The potential of on-chip multiprocessing for QCD machinesProceedings of the 12th international conference on High Performance Computing10.1007/11602569_41(386-397)Online publication date: 18-Dec-2005
https://dl.acm.org/doi/10.1007/11602569_41
Adler MByers JSnyder LLeiserson C(1994)AT2 bounds for a class of VLSI problems and string matchingProceedings of the sixth annual ACM symposium on Parallel algorithms and architectures10.1145/181014.181092(140-146)Online publication date: 1-Aug-1994
https://dl.acm.org/doi/10.1145/181014.181092
Alnuweiri H(1993)A New Class of Optimal Bounded-Degree VLSI Sorting NetworksIEEE Transactions on Computers10.1109/12.27729942:6(746-752)Online publication date: 1-Jun-1993
https://dl.acm.org/doi/10.1109/12.277299
Alia GMartinelli E(1993)On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue RepresentationIEEE Transactions on Computers10.1109/12.23848642:8(962-967)Online publication date: 1-Aug-1993
https://dl.acm.org/doi/10.1109/12.238486
Bilardi GPreparata F(1989)Size-time complexity of Boolean networks for prefix computationsJournal of the ACM10.1145/62044.6205236:2(362-382)Online publication date: 1-Apr-1989
https://dl.acm.org/doi/10.1145/62044.62052
Cole RSiegel A(1988)Optimal VLSI circuits for sortingJournal of the ACM10.1145/48014.4801735:4(777-809)Online publication date: 1-Oct-1988
https://dl.acm.org/doi/10.1145/48014.48017
Show More Cited By

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents