Trace software pipelining

Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Trace Software Pipelining, targeted to the instruction-level parallel processors such as Very Long Instruction Word (VLIW) and superscalar machines. Trace software pipelining applies a global code scheduling technique to compact the original loop body. The resulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or can be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promising in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.