article

Random variability modeling and its impact on scaled CMOS circuits

Authors:

Samatha Gummalla,

Chaitali Chakrabarti,

Yu CaoAuthors Info & Claims

Journal of Computational Electronics, Volume 9, Issue 3-4

Pages 108 - 113

https://doi.org/10.1007/s10825-010-0336-5

Published: 01 December 2010 Publication History

Abstract

Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (V _th) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design.

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Cited By

Tan XDomanski PBanerjee SChakrabarty KAmrouch HHu JGarg SLin Y(2024)ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging EffectsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685968(1-9)Online publication date: 9-Sep-2024
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Published In

cover image Journal of Computational Electronics

Journal of Computational Electronics Volume 9, Issue 3-4

December 2010

166 pages

ISSN:1569-8025

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Copyright © Copyright © 2010 Springer Science+Business Media LLC.

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 December 2010

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Cited By

Tan XDomanski PBanerjee SChakrabarty KAmrouch HHu JGarg SLin Y(2024)ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging EffectsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685968(1-9)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685968
Shaik JPicardo SSinghal SGoel N(2024)Reliability-aware design of Integrate-and-Fire silicon neuronsIntegration, the VLSI Journal10.1016/j.vlsi.2023.10210194:COnline publication date: 1-Jan-2024
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https://dl.acm.org/doi/10.1016/j.vlsi.2020.01.006
Sriram SBindu B(2020)A physics-based model for LER-induced threshold voltage variations in double-gate MOSFETJournal of Computational Electronics10.1007/s10825-020-01474-w19:2(622-630)Online publication date: 1-Jun-2020
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Gojman BNalmela SMehta NHowarth NDehon A(2014)GROK-LABACM Transactions on Reconfigurable Technology and Systems10.1145/25978897:4(1-23)Online publication date: 29-Dec-2014
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Wagner MWunderlich HMacii E(2013)Efficient variation-aware statistical dynamic timing analysis for delay test applicationsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485357(276-281)Online publication date: 18-Mar-2013
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