Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
article

Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)

Published: 01 June 2018 Publication History

Abstract

Tunnel field-effect transistors have shown great potential given their good scalability and low leakage current. However, they are associated with some drawbacks, including ambipolar behavior and low ON-state current relative to the MOSFET. To overcome these problems, a novel junctionless gate-all-around TFET (JL GAA TFET) is proposed. The proposed device employs a two-dimensional model by solving Poisson's equation in 2D. The results are verified with the assistance of Sentaurus Device simulation software. The electrical and electrostatic characteristics of the JL GAA TFET, including its surface potential, energy band, electric field, threshold voltage and drain current, are studied using models and simulations. The impact of various gate insulator materials is also studied using the model, and the transfer current of the JL GAA TFET is compared with that of a different type of FET device. The JL GAA TFET exhibits a high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio ($$\sim 10^{9}$$~109) and a subthreshold slope of 28 mV/decade at room temperature for the high-kdielectric gate insulator material $$(\hbox {TiO}_{2})$$(TiO2). With regard to the use of the device in switching applications, the JL GAA TFET appears to be a good candidate.

References

[1]
Barraud, S., Berthome, M., Coquand, R., Casse, M., Ernst, T., Samson, M.P., Perreau, P., Bourdelle, K.K., Faynot, O., Poiroux, T.: Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron. Device Lett. 33(9), 1225---1227 (2012)
[2]
Coquand, R., Barraud, S., Cassé, M., Leroux, P., Vizioz, C., Comboroure, C., Perreau, P., Ernt, E., Sanson, M.P., Alvaro, V.M., Tabone, C., Barnola, S., Munteanu, D., Ghibaudo, G., Monfray, S., Boeuf, F., Poiroux, T.: Scaling of high-K/metal-gate trigate SOI nanowire transistors down to 10nm width. In: Proceedings of the ULIS Conference, pp. 37---40 (2012)
[3]
Tachi, K., Cassé, M., Barraud, S., Dupré, C., Hubert, A., Vulliet, N., Faivre, M.E., Vizioz, C., Carabasse, C., Delaye, V., Hartmann, J.M., Iwai, H., Cristoloveanu, S., Faynot, O., Ernst, T.: Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors. In: IEDM Technical Digest, pp. 94---95 (2009)
[4]
Colinge, J.-P.: Multiple-gate soi mosfets. Solid State Electron. 48(6), 897---905 (2004)
[5]
Kuo, P.Y., Lu, Y.H., Chao, T.S.: High-performance GAA sidewall-damascened sub-10-nm in situ nÞ-doped Poly-Si NWs channels junctionless FETs. IEEE Trans. Electron. Devices 61(11), 3821---3826 (2014)
[6]
Jhaveri, R., Nagavarapu, V., Woo, J.C.S.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron. Devices 58(1), 80---86 (2011)
[7]
Tura, A., Zh Zhang, P., Liu, Y.H., Xie, J.C.S.Woo: Vertical silicon p-n-p-n tunnel nMOSFET with MBE-grown tunneling junction. IEEE Trans. Electron. Devices 58(7), 1907---1913 (2011)
[8]
Rahimian, M., Orouji, Ali A.: Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation. Superlattices Microstruct. 50, 667---679 (2011)
[9]
Orouji, A.A., Rahimian, M.: Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism. Curr. Appl. Phys. 12, 1366---1371 (2012)
[10]
Wang, P.F., Hilsenbeck, K., Nirschl, Th, Oswald, M., Stepper, Ch., Weis, M., Landsiedel, D.S., Hansch, W.: Complementary tunneling transistor for low power application. Solid State Electron. 48, 2281---2286 (2004)
[11]
Toh, E.H., Wang, G.H., Chan, L., Sylvester, D., Heng, ChH, Samudra, G.S., Yeo, YCh.: Device design and scalability of a double-gate tunneling field-effect transistor with silicon-germanium source. Jpn. J. Appl. Phys. 47(4), 2593---2597 (2008)
[12]
Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-K gate dielectric. IEEE Trans. Electron. Devices 54(7), 1725---1733 (2007)
[13]
Choi, W.Y., Park, B.G., Lee, J.D., Liu, T.J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron. Device Lett. 28(8), 743---745 (2007)
[14]
Narendar, V., Rai, S., Tiwari, S., Mishra, R.A.: A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications. Superlattices Microstruct. 100(12), 274---289 (2016)
[15]
Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373), 329---337 (2011)
[16]
Fiore, A., Franco, J., Cho, M., Crupi, F., Strangio, S., Roussel, P.J., Rooyackers, R., Collaert, N., Linten, D.: Single defect discharge events in vertical-nanowire tunnel FETs. IEEE Trans. Device Mater. Reliab. 17(1), 253---258 (2017)
[17]
Abdi, D.B., Kumar, M.J.: PNPN tunnel FET with controllable drain side tunnel barrier width: proposal and analysis. Superlattices Microstruct. 86, 121---125 (2015)
[18]
Sze, S.M., Ng, K.K.: Physics of Semiconductor Devices. Wiley, London (2006)
[19]
Björk, M.T., Knoch, J., Schmid, H., Riel, H., Riess, W.: Silicon nanowire tunneling field effect transistors. Appl. Phys. Lett. 92, 193504 (2008)
[20]
Damrongplasit, N., Kim, S.H., Liu, T.J.K.: Study of random dopant fluctuation induced variability in the raised-Ge-source TFET. IEEE Electron. Device Lett. 34(2), 184---186 (2013)
[21]
Sahay, S., Kumar, M.J.: Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using hetero dielectric BOX. IEEE Trans. Electron. Devices 62(11), 3882---3886 (2015)
[22]
Abdi, D.B., Kumar, M.J.: Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J. Electron. Devices Soc. 2(6), 187---190 (2014)
[23]
Anghel, C., Chilagani, P., Amara, A., Vladimirescu, A.: Tunnel field effect transistor with increased on current, low-k spacer and high-k dielectric. Appl. Phys. Lett. 96, 122104 (2010)
[24]
Jhaveri, R., Nagavarapu, V., Woo, J.C.S.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron. Devices 58(1), 80---86 (2011)
[25]
Chang, H.Y., Adams, B., Chien, P.Y., Li, J., Woo, J.C.S.: Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing. IEEE Trans. Electron. Devices 60(1), 92---96 (2013)
[26]
Colinge, J.-P., Lee, C.-W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Ravazi, P., O'Neill, B., Blake, A., White, M., Kelleher, A.-M., McCarthy, B., Murphy, R.: Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225---229 (2010)
[27]
Jin, X., Xi, L., Wu, M., Rongyan, C., Lee, J.-H., Lee, J.-H.: A unified analytical continuous current model applicable to accumulation mode (junctionless) and inversion mode MOSFETs with symmetric and asymmetric double-gate structures. Solid State Electron. 79, 206---209 (2013)
[28]
Gundapaneni, S., Ganguly, S., Kottantharayil, A.: Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron. Device Lett. 32, 261---263 (2011)
[29]
Su, C.-J., Tsai, T.-I., Liou, Y.-L., Lin, Z.-M., Lin, H.-C., Chao, T.-S.: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron. Device Lett. 32, 521---523 (2011)
[30]
Ghosh, B., Akram, M.W.: Junctionless tunnel field effect transistor. IEEE Electron. Device Lett. 34, 584---586 (2013)
[31]
Bal, P., Akram, M.W., Mondal, P., Ghosh, B.: Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET). J. Comput. Electron. 12, 782---789 (2013)
[32]
Robertson, J.: High dielectric constant oxides. Eur. Phys. J. Appl. Phys. 28(3), 265---291 (2004)
[33]
TCAD Sentaurus Device User Manual, Synopsys, CA (2013)
[34]
Dash, S., Mishra, G.P.: A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET). Superlattices Microstruct. 86, 211---220 (2015)
[35]
Luong, G.V., Strangio, S., Tiedemannn, A., Lenk, S., Trellenkamp, S., Bourdelle, K.K., Zhao, Q.T., Mantl, S.: Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages. Solid State Electron. 115, 152---159 (2016)
[36]
Lin, S.C., Kuo, J.B.: Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/Sidewall oxide spacer structure. IEEE Trans. Electron. Devices 50(12), 2559---2564 (2013)
[37]
Ding, Z., hu, G., Gu, J., Liu, R., Wang, L., Tang, T.: An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs. Microelectron. J. 42(3), 515---519 (2011)
[38]
Kane, E.O.: Zener tunneling in semiconductors. J. Phys. Chem. Solids 12(2), 181---188 (1960)
[39]
Solomon, P.M., Jopling, J., Frank, D.J., D'Emic, C., Dokumaci, O., Ronsheim, P., Haensch, W.E.: Universal tunneling behavior in technologically relevant P/N junction diodes. J. Appl. Phys. 95(10), 5800---5812 (2004)
[40]
Wan, J., Royer, C.L., Zaslavsky, A., Cristoloveanu, S.: A tunneling field effect transistor model combining interband tunneling with channel transport. J. Appl. Phys. 110(10), 104503-1---104503-7 (2011)
  1. Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image Journal of Computational Electronics
      Journal of Computational Electronics  Volume 17, Issue 2
      June 2018
      390 pages

      Publisher

      Springer-Verlag

      Berlin, Heidelberg

      Publication History

      Published: 01 June 2018

      Author Tags

      1. Analytical model
      2. Gate-all-around
      3. Junctionless
      4. Subthreshold slope (SS)
      5. TCAD
      6. Tunnel FET

      Qualifiers

      • Article

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • 0
        Total Citations
      • 0
        Total Downloads
      • Downloads (Last 12 months)0
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 09 Feb 2025

      Other Metrics

      Citations

      View Options

      View options

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media