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A highly efficient dynamic router for application-oriented network on chip

Published: 01 July 2018 Publication History

Abstract

With the number of processor cores increasing in chip multiprocessors, the network on chip becomes a reliable structure with its perfect parallel communication performance. The traditional static router suffers a bad performance because of low buffer utilization for application-oriented network on chip. In this paper, a dynamic router which can take into account the unbalanced traffic for application-oriented network on chip is proposed. The router combines the inter-port and intra-port buffer allocation mechanism, which makes efficient use of buffer resources and avoids the head of line blocking. Furthermore, the proposed router can solve the problem of unbalanced load effectively between different ports on the same router. Simulation results show that the on-chip routers balance traffic between ports and increase the buffer utilization by 21.8%, thus optimizing delay and throughput performance for application-oriented network on chip.

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    Published In

    cover image The Journal of Supercomputing
    The Journal of Supercomputing  Volume 74, Issue 7
    July 2018
    583 pages

    Publisher

    Kluwer Academic Publishers

    United States

    Publication History

    Published: 01 July 2018

    Author Tags

    1. Buffer allocation
    2. Network on chip
    3. Router

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    • (2020)A novel packet exchanging strategy for preventing HoL-blocking in fat-treesCluster Computing10.1007/s10586-019-02940-223:2(461-482)Online publication date: 1-Jun-2020

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