article

Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

Authors:

Louise Crockett,

Robert StewartAuthors Info & Claims

Journal of Signal Processing Systems, Volume 69, Issue 1

Pages 75 - 85

https://doi.org/10.1007/s11265-011-0646-2

Published: 01 October 2012 Publication History

Abstract

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.

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Cited By

Marconi T(2018)Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arraysComputers and Electrical Engineering10.1016/j.compeleceng.2013.07.00440:4(1215-1237)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2013.07.004

Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

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Information

Published In

cover image Journal of Signal Processing Systems

Journal of Signal Processing Systems Volume 69, Issue 1

October 2012

106 pages

ISSN:1939-8018

EISSN:1939-8115

Issue’s Table of Contents

Copyright © Copyright © 2012 Springer Science+Business Media, LLC.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 October 2012

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Cited By

Marconi T(2018)Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arraysComputers and Electrical Engineering10.1016/j.compeleceng.2013.07.00440:4(1215-1237)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2013.07.004

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