High Reliability Soft Error Hardened Latch Designfor Nanoscale CMOS Technology using PVT Variation
Authors: 
T. Dhanushya, T. LathaAuthors Info & Claims
T. Dhanushya, T. LathaAuthors Info & ClaimsPages 1471 - 1487
Abstract
In this paper, a soft error hardened circuit with the aim ofavoiding and detecting-correctingthe soft error strikesat the same timing phase is proposed for high-speed memory applications. The proposed design is completely immune to multiple soft errors occurring in any of the nodes. The avoidance part and detection-correction part are the two major parts that tolerate multiple particle strikes. The proposed design can detect and correct a single particle strike at single node and at multiple nodes.A set of simulations are made in CMOS technology to validate the proposed circuit in terms of delay, power, and area overheads which are the main requirements of VLSI design. Compared with other techniques it is shown that the proposed circuit achieves 1.124 μm power consumption, and142.68ps delay overheads. The work also investigates about Monte Carlo simulations along with the impact of process, voltage and temperature (PVT) variations and shows that the proposed circuit is highly reliable and less sensitive to soft errors compared with other existing soft error latches.
References
[1]
Argyrides CA, Reviriego P, Pradan DK, and Maestro AK Matrix-based codes for adjacent error correction IEEE Transactions on Nuclear Science 2010 57 4 2106-2111
[2]
Neuberger G, De Lima Kastensmidt FG, and Reis R An automatic technique for optimizing reed-solomon codes to improve fault tolerance in memories IEEE Design & Test of Computers 2005 22 1 50-58
[3]
Ming Z, Yi XL, Chang L, and Wei ZJ Reliability of memories protected by multibit error correction codes against MBUs IEEE Transactions on Nuclear Science 2011 58 1 289-295
[4]
Xuan SX, Li N, and Tong J SEU hardened flip-flop based on dynamic logic IEEE Transactions on Nuclear Science 2013 60 5 3932-3936
[5]
Montesinos, P., Liu, W., & Torrellas, J. (2007). Using register lifetime predictions to protect register files against soft errors. In Proceedings of37th Annual IEEE/FIP International Conference on Dependable Systems and Networks (DSN’07) (pp. 286-296). Edinburgh, UK
[6]
Omana M, Rossi D, and Metra C High performance robust latches IEEE Transactions on Computers 2010 59 11 1455-1465
[7]
Nan H and Choi K High performance low cost and robust soft error tolerant latch designs for nanoscale CMOS technology IEEE Transactions on Circuits & Systems 2012 59 7 1445-1457
[8]
Trang Dang LD, Kim JS, and Chang IJ We-Quatro: Radiation Hardened SRAM cell with parametric process variation tolerance IEEE Transactions on Nuclear Science 2017 60 5 2489-2496
[9]
Das, S., Tokunaga, C., Pant, S., Ma, W. H., Kalaiselvan, S., Lai, K., Bull, D. M. & Blaauw, D. T. (2009). RazorII: in situ error detection and correction for PVT and SER tolerance. IEEE Journal of Solid-State Circuits, 44(1), 32–48
[10]
Lin Y, Zwolinski M, and Halak B A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016 24 5 1688-1701
[11]
Zhang M, Mitra S, Mark TM, Seifert N, Wang NJ, Shi Q, Kim KS, Shanbhag NR, and Patel SJ Sequential element design with built-in soft error resilience IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2006 14 12 1368-1378
[12]
Shirinzadeh, S., & Asli, R. N. (2012). A Novel soft error hardened latch design in90nm CMOS. In Proceedings of 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012) (pp. 60-63). Shiraz, Iran
[13]
Lin S, Kim YB, and Lombardi F Design and performance evaluation of radiation hardened latches for nanoscalecmos IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2011 19 7 1315-1319
[14]
She X, Li N, and Tong J SEU tolerant latch based on error detection IEEE Transactions on Nuclear Science 2012 59 1 211-214
[15]
Fazeli M, Miremadi SG, Ejlali A, and Patooghy A Low energy single event upset/single event transient tolerant latch for deep submicron technologies IET Computers & Digital Techniques 2009 3 3 289-303
[16]
Rajaei R, Tabandeh M, and Fazeli M Single event multiple upset (semu) tolerant latch designs in presence of process and temperature variations Journal of Circuits Systems and Computers 2014 24 1 1-30
[17]
Li HC, Xiao LY, Li J, and Qi CH High robust and cost effective double node upset tolerant latch design for nanoscalecmos technology Microelectronics Reliability 2019 93 89-97
[18]
Li, J., Xiao, L. Y., Li, H. C., & Qi, C. H. (2018). A low-overhead radiation hardened design flip-flop for soft error detection. In Proceedings of 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). Qingdao, China
[19]
Chaudhry I and Anand B High performance energy efficient radiation hardened latch for low voltage applications Integration 2019 66 119-127
[20]
Anajemba JH, Ansere JA, Sam F, Iwendi C, and Srivastava G Optimal soft error mitigation in wireless communication using approximate logic circuits Sustainable Computing: Informatics and Systems 2021 30 100521
[21]
Wey, I. C., Chen, C. H., Fang, S. Z., & Chou, H. J. (2019). Soft-event-upset and soft-event-transient tolerant cmos circuit design for low-voltage low-power wireless IoT applications. In Proceedings of Eleventh International Conference on Ubiquitous and Future Networks (ICUFN) (pp. 179-181). Zagreb Croatia
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Publication History
Published: 31 October 2022
Accepted: 30 August 2022
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