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TTAs: missing the ILP complexity wall

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Henk CorporaalAuthors Info & Claims

Journal of Systems Architecture: the EUROMICRO Journal, Volume 45, Issue 12-13

Pages 949 - 973

https://doi.org/10.1016/S1383-7621(98)00046-0

Published: 01 June 1999 Publication History

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Hepola KMultanen JJääskeläinen P(2024)Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set ModeIEEE Transactions on Computers10.1109/TC.2023.333731373:2(560-573)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TC.2023.3337313
Schneider KBhagyanath A(2023)Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann ArchitecturesACM Transactions on Embedded Computing Systems10.1145/360786922:5(1-25)Online publication date: 26-Sep-2023
https://dl.acm.org/doi/10.1145/3607869
Hepola KMultanen JJääskeläinen P(2022)Dual-IS: Instruction Set Modality for Efficient Instruction Level ParallelismArchitecture of Computing Systems10.1007/978-3-031-21867-5_2(17-32)Online publication date: 13-Sep-2022
https://dl.acm.org/doi/10.1007/978-3-031-21867-5_2
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cover image Journal of Systems Architecture: the EUROMICRO Journal

Journal of Systems Architecture: the EUROMICRO Journal Volume 45, Issue 12-13

Special double issue on microprocessor architecture

June 1999

225 pages

ISSN:1383-7621

Editors:
Mariagiovanna Sami
Politecnico di Milano, Milana, Italy
,
Lutz Richter
Univ. Zürich-Irchel, Zürich, Switzerland
,
A. De Gloria
Univ. of Genoa, Genoa, Italy

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Elsevier North-Holland, Inc.

United States

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Published: 01 June 1999

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Hepola KMultanen JJääskeläinen P(2024)Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set ModeIEEE Transactions on Computers10.1109/TC.2023.333731373:2(560-573)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TC.2023.3337313
Schneider KBhagyanath A(2023)Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann ArchitecturesACM Transactions on Embedded Computing Systems10.1145/360786922:5(1-25)Online publication date: 26-Sep-2023
https://dl.acm.org/doi/10.1145/3607869
Hepola KMultanen JJääskeläinen P(2022)Dual-IS: Instruction Set Modality for Efficient Instruction Level ParallelismArchitecture of Computing Systems10.1007/978-3-031-21867-5_2(17-32)Online publication date: 13-Sep-2022
https://dl.acm.org/doi/10.1007/978-3-031-21867-5_2
Bhagyanath ASchneider KTalpin J(2016)Optimal compilation for exposed datapath architectures with buffered processing units by SAT solversProceedings of the 14th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343414.3343435(143-152)Online publication date: 18-Nov-2016
https://dl.acm.org/doi/10.5555/3343414.3343435
Anjum OAli MPitkänen TNurmi J(2014)Transport triggered architecture to perform carrier synchronization for LTEACM Transactions on Embedded Computing Systems10.1145/256003613:4(1-15)Online publication date: 10-Mar-2014
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Goel NKumar APanda P(2014)Shared-port register file architecture for low-energy VLIW processorsACM Transactions on Architecture and Code Optimization10.1145/253339711:1(1-32)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2533397
Patyk TSalmela PPitkänen TJääskeläinen PTakala J(2011)Design Methodology for Offloading Software Executions to FPGAJournal of Signal Processing Systems10.5555/2070637.207065065:2(245-259)Online publication date: 1-Nov-2011
https://dl.acm.org/doi/10.5555/2070637.2070650
Thuresson MSjälander MBjörk MSvensson LLarsson-Edefors PStenstrom P(2009)FlexCoreJournal of Signal Processing Systems10.1007/s11265-008-0172-z57:1(5-19)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1007/s11265-008-0172-z
Kim HWills DWills L(2005)Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand TransportProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 15 - Volume 1610.1109/IPDPS.2005.423Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1109/IPDPS.2005.423
Pillai SJacome M(2003)Compiler-Directed ILP Extraction for Clustered VLIW/EPIC MachinesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022764Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022764

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A fill-unit approach to multiple instruction issue

Enhancing instruction scheduling with a block-structured ISA

A low-complexity microprocessor design with speculative pre-execution

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A fill-unit approach to multiple instruction issue

Enhancing instruction scheduling with a block-structured ISA

A low-complexity microprocessor design with speculative pre-execution

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