article

Dataflow Architectures for GALS

Authors:

Deepak Mathaikutty,

Sandeep ShuklaAuthors Info & Claims

Electronic Notes in Theoretical Computer Science (ENTCS), Volume 200, Issue 1

Pages 33 - 50

https://doi.org/10.1016/j.entcs.2008.02.005

Published: 01 February 2008 Publication History

Abstract

In Kahn process network (KPN), the processes (nodes) communicate by unbounded unidirectional FIFO channels (arcs), with the property of non-blocking writes and blocking reads on the channels. KPN provides a semantic model of computation, where a computation can be expressed as a set of asynchronously communicating processes. However, the unbounded FIFO based asynchrony is not realizable in practice and hence requires refinement in real hardware. In this work, we start with KPN as the model of computation for GALS, and discuss how different GALS architectures can be realized. We borrow some ideas from existing dataflow architectures for our GALS designs.

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Digital Library

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Suhaib, S., Mathaikutty, D., Berner, D. and Shukla, S., Validating families of latency insensitive protocols. IEEE Transactions on Computers. v55 i11. 1391-1401.

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Cited By

Bezati ECasale-Brunet SMattavelli MJanneck J(2017)Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721536:4(699-703)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597215
Burns FSokolov DYakovlev ANebel WAtienza D(2015)GALS synthesis and verification for xMAS modelsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757141(1419-1424)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757141
Cong JLiu ALiu BRosenstiel WWakabayashi K(2009)A variation-tolerant scheduler for better than worst-case behavioral synthesisProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629467(221-228)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629467

Index Terms

Dataflow Architectures for GALS
1. Hardware

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Published In

cover image Electronic Notes in Theoretical Computer Science (ENTCS)

Electronic Notes in Theoretical Computer Science (ENTCS) Volume 200, Issue 1

February, 2008

86 pages

ISSN:1571-0661

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Copyright © Elsevier B.V. © 2008.

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Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 February 2008

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Cited By

Bezati ECasale-Brunet SMattavelli MJanneck J(2017)Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.259721536:4(699-703)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2597215
Burns FSokolov DYakovlev ANebel WAtienza D(2015)GALS synthesis and verification for xMAS modelsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757141(1419-1424)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757141
Cong JLiu ALiu BRosenstiel WWakabayashi K(2009)A variation-tolerant scheduler for better than worst-case behavioral synthesisProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629467(221-228)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629467

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