A design of 10-bit, 10MS/s Pipelined ADC with Time-interleaved SAR
Authors: 
ByeongGi Jang, Abbas Syed Hayder, SungHan Do, SungHun Cho, DongSoo Lee, YoungGun Pu, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon LeeAuthors Info & Claims
ByeongGi Jang, Abbas Syed Hayder, SungHan Do, SungHun Cho, DongSoo Lee, YoungGun Pu, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon LeeAuthors Info & ClaimsAbstract
This paper presents a 10-bit, 10MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28mW under a supply voltage of 1.2V was fabricated in 0.13m CMOS and occupies an area of only 0.21mm2.
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Published: 01 April 2017
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