research-article

An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory

Authors:

N. PlerosAuthors Info & Claims

Optical Switching and Networking, Volume 22, Issue C

Pages 54 - 68

https://doi.org/10.1016/j.osn.2016.05.001

Published: 01 November 2016 Publication History

Abstract

We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection system is realized through Wavelength-Division-Multiplexed optical interfaces connecting the shared cache with the cores and the Main-Memory via spatial-multiplexed waveguides. Evaluating the proposed approach, we realize system-level simulations of a wide-range parallel workloads using Gem5. Optical cache architecture is compared against the conventional one that uses dedicated on-chip Level-1 electronic caches and a shared Level-2 cache. Results show significant Level-1 miss rate reduction of up to 96% for certain cases; on average, a performance speed-up of 19.4% or cache capacity requirements reduction of ~63% is attained. Combined with high-bandwidth CPU-Dynamic Random Access Memory (DRAM) bus solutions based on optical interconnects, the proposed design is a promising architecture bridging the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies. We present an optical-bus CMP architecture where an optical shared cache is used.The optical cache resides in a separate chip and no on-chip cache is required.The CPU-DRAM communication is realized completely in the optical domain.Significant L1 miss rate reduction of up to 96% for certain cases is attained.Average speed-up of 19.4% or capacity requirements reduction of ~63% is attained.

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Cited By

Han HAlexoudi TVagionas CPleros NHardavellas N(2022)A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/353101218:4(1-28)Online publication date: 20-Apr-2022
https://dl.acm.org/doi/10.1145/3531012
Han HAlexoudi TVagionas CPleros NHardavellas N(2021)Pho$Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1109/ISLPED52811.2021.9502487(1-6)Online publication date: 26-Jul-2021
https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502487

An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
1. General and reference
  1. Cross-computing tools and techniques
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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cover image Optical Switching and Networking

Optical Switching and Networking Volume 22, Issue C

November 2016

127 pages

ISSN:1573-4277

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Copyright © Elsevier B.V.

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Elsevier Science Publishers B. V.

Netherlands

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Published: 01 November 2016

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Han HAlexoudi TVagionas CPleros NHardavellas N(2022)A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/353101218:4(1-28)Online publication date: 20-Apr-2022
https://dl.acm.org/doi/10.1145/3531012
Han HAlexoudi TVagionas CPleros NHardavellas N(2021)Pho$Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1109/ISLPED52811.2021.9502487(1-6)Online publication date: 26-Jul-2021
https://dl.acm.org/doi/10.1109/ISLPED52811.2021.9502487

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