article

Discrete cosine and sine transforms: regular algorithms and pipeline architectures

Authors:

Jari A. Nikara,

Jarmo H. Takala,

Jaakko T. AstolaAuthors Info & Claims

Signal Processing, Volume 86, Issue 2

Pages 230 - 249

https://doi.org/10.1016/j.sigpro.2005.05.014

Published: 01 February 2006 Publication History

Abstract

In this paper, regular fast algorithms for discrete cosine transform (DCT) and discrete sine transform (DST) of types II-IV are proposed and mapped onto pipeline architectures. The algorithms are based on the factorization of transform matrices described earlier by Wang. The regular structures of the algorithms are advantageous when mapping them onto hardware although such algorithms do not reach the theoretical lower bound on multiplicative complexity. Instead, the algorithms lend themselves for vertical mapping resulting in area-efficient pipeline structures. A unified pipeline architecture supporting both the DCT-II and its inverse is implemented with data path synthesis for proving the feasibility and estimating the performance. The latency of an ASIC implementation is 94 cycles while operating at 250 MHz frequency.

References

[1]

{1} A. Viholainen, J. Alhava, M. Renfors, Implementation of parallel cosine and sine modulated filter banks for equalized transmultiplexer systems, in: Proceedings of the IEEE International Conference on Acoustic, Speech, Signal Processing, vol. 6, Salt Lake City, UT, USA, May 7-11, 2001, pp. 3625-3628.

[2]

{2} Z. Wang, Fast algorithms for the discrete W transform and for the discrete Fourier transform, IEEE Trans. Acoust. Speech Signal Process. 32 (4) (August 1984) 803-816.

[3]

{3} C. Loeffler, A. Ligtenberg, G.S. Moschytz, Practical fast 1- D DCT algorithms with 11 multiplications, in: Proceedings of the IEEE International Conference on Acoustic, Speech, Signal Processing, vol. 2, Glasgow, UK, May 23-26, 1989, pp. 988-991.

[4]

{4} Z. Wang, Fast discrete sine transform algorithms, Signal Process. 19 (2) (February 1990) 91-102.

Digital Library

[5]

{5} Z. Wang, Pruning the fast discrete cosine transform, IEEE Trans. Commun. 39 (5) (May 1991) 640-643.

[6]

{6} J. Astola, D. Akopian, Architecture-oriented regular algorithms for discrete sine and cosine transforms, IEEE Trans. Signal Process. 47 (4) (April 1999) 1109-1124.

Digital Library

[7]

{7} J. Takala, D. Akopian, J. Astola, J. Saarinen, Constant geometry algorithm for discrete cosine transform, IEEE Trans. Signal Process. 48 (6) (June 2000) 1840-1843.

Digital Library

[8]

{8} J. Kwak, J. You, One- and two-dimensional constant geometry fast cosine transform algorithms and architectures, IEEE Trans. Signal Process. 47 (7) (July 1999) 2023-2034.

Digital Library

[9]

{9} S.-F. Hsiao, J.-M. Tseng, New matrix formulation for two-dimensional DCT/IDCT computation and its distributed-memory VLSI implementation, IEE Proc.-Vis. Image Process. 149 (2) (April 2002) 97-107.

[10]

{10} P.-Z. Lee, F.-Y. Huang, Restructured recursive DCT and DST algorithms, IEEE Trans. Signal Process. 42 (7) (July 1994) 1600-1609.

Digital Library

[11]

{11} J. Nikara, J. Takala, D. Akopian, J. Saarinen, Pipeline architecture for DCT/IDCT, in: Proceedings of the IEEE International Symposium on Circuits Systems, vol. 4, Sydney, Australia, May 6-9, 2001, pp. 902-905.

[12]

{12} J. Takala, J. Nikara, Unified pipeline architecture for discrete sine and cosine transforms of type IV, in: Proceedings of the Third International Conference on Information Communication and Signal Processing, Singapore, October 15-18, 2001.

[13]

{13} J. Takala, J. Nikara, K. Punkka, Pipeline architecture for two-dimensional discrete cosine transform and its inverse, in: Proceedings of the Ninth International Conference on Electronics Circuits Systems, vol. 3, Dubrovnik, Croatia, September 15-18, 2002, pp. 947-950.

[14]

{14} E.W. Weisstein. Matrix direct sum From MathWorld--A Wolfram Web Resource, 2004. {Online} Available: http:// mathworld.wolfram.com/MatrixDirectSum.html

[15]

{15} J. Granata, M. Conner, R. Tolimieri, Recursive fast algorithms and the role of the tensor product, IEEE Trans. Signal Process. 40 (12) (December 1992) 2921-2930.

[16]

{16} J. Takala, T. Järvinen, Stride permutation access in interleaved memory systems, in: S.S. Bhattacharyya, E.F. Deprettere, J. Teich (Eds.), Domain-Specific Multiprocessors--Systems, Architectures, Modeling, and Simulation, Marcel Dekker, New York, USA, 2004, pp. 63-84 (Chapter 4).

[17]

{17} M. Davio, Kronecker products and shuffle algebra, IEEE Trans. Comput. 30 (2) (February 1981) 116-125.

Digital Library

[18]

{18} J. Nikara, J. Takala, Unified pipeline architecture for in-order 8 × 8 DCT and IDCT, in: Proceedings of the 5th World Multiconference Systemics Cybernetics Informatics, vol. 4, Orlando, FL, USA, July 22-25, 2001, pp. 30-35.

[19]

{19} C.B. Shung, H.-D. Lin, R. Cypher, P.H. Siegel, H.K. Thapar, Area-efficient architectures for the Viterbi algorithm I. Theory, IEEE Trans. Commun. 41 (4) (April 1993) 636-644.

[20]

{20} C.B. Shung, H.-D. Lin, R. Cybher, P.H. Siegel, H.K. Thapar, Area-efficient architectures for Viterbi algorithm II. Applications, IEEE Trans. Commun. 41 (5) (May 1993) 802-807.

[21]

{21} A. Madisetti, A.N. Wilson, A 100 MHz 2-D 8 × 8 DCT/IDCT processor for HDTV applications, IEEE Trans. Circuits Syst. Video Technol. 5 (2) (April 1995) 158-165.

Digital Library

[22]

{22} Y.-P. Lee, L.-G. C, T.-H. Chen, M.-J. Chen, C.-W. Ku, A cost-effective architecture for 8 × 8 two-dimensional DCT/ IDCT using direct method, IEEE Trans. Circuits Syst. Video Technol. 7 (3) (June 1997) 459-467.

Digital Library

[23]

{23} Y. Katayama, T. Kitsuki, Y. Ooi, A block processing unit in single-chip MPEG-2 video encoder LSI, J. VLSI Signal Process. 22 (1) (August 1999) 59-64.

Digital Library

[24]

{24} H. Lim, V. Piuri, E.E. Swartzlander, A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms, IEEE Trans. Comput. 49 (12) (December 2000) 1297-1309.

Digital Library

Cited By

Milder PFranchetti FHoe JPüschel M(2012)Computer Generation of Hardware for Linear Digital Signal Processing TransformsACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954717:2(1-33)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159547

Index Terms

Discrete cosine and sine transforms: regular algorithms and pipeline architectures

Recommendations

The discrete fractional cosine and sine transforms

This paper is concerned with the definitions of the discrete fractional cosine transform (DFRCT) and the discrete fractional sine transform (DFRST). The definitions of DFRCT and DFRST are based on the eigen decomposition of DCT and DST kernels. This is ...
Invariant spaces and cosine transforms DCT - 2 and DCT - 6
CompSysTech '04: Proceedings of the 5th international conference on Computer systems and technologies

In paper two types of the discrete cosine (and sine) transforms (DCT/DST) are analyzed. These transforms are useful for many applications. It is shown that if an operator, connected with the Discrete Fourier Transform (DFT), is referred to an ...
Fractional cosine, sine, and Hartley transforms

In previous papers, the Fourier transform (FT) has been generalized into the fractional Fourier transform (FRFT), the linear canonical transform (LCT), and the simplified fractional Fourier transform (SFRFT). Because the cosine, sine, and Hartley ...

Comments

Information & Contributors

Information

Published In

cover image Signal Processing

Signal Processing Volume 86, Issue 2

February 2006

209 pages

ISSN:0165-1684

Issue’s Table of Contents

Publisher

Elsevier North-Holland, Inc.

United States

Publication History

Published: 01 February 2006

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 26 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Milder PFranchetti FHoe JPüschel M(2012)Computer Generation of Hardware for Linear Digital Signal Processing TransformsACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954717:2(1-33)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159547

View Options

View options

Figures

Tables

Media

View Issue’s Table of Contents