article

Implementation and evaluation of a microthread architecture

Authors:

C. R. Jesshope,

M. LankampAuthors Info & Claims

Journal of Systems Architecture: the EUROMICRO Journal, Volume 55, Issue 3

Pages 149 - 161

https://doi.org/10.1016/j.sysarc.2008.07.001

Published: 01 March 2009 Publication History

Abstract

Future many-core processor systems require scalable solutions that conventional architectures currently do not provide. This paper presents a novel architecture that demonstrates the required scalability. It is based on a model of computation developed in the AETHER project to provide a safe and composable approach to concurrent programming. The model supports a dynamic approach to concurrency that enables self-adaptivity in any environment so the model is quite general. It is implemented here in the instruction set of a dynamically scheduled RISC processor and many such processors form a microgrid. Binary compatibility over arbitrary clusters of such processors and an inherent scalability in both area and performance with concurrency exploited make this a very promising development for the era of many-core chips. This paper introduces the model, the processor and chip architecture and its emulation on a range of computational kernels. It also estimates the area of the structures required to support this model in silicon.

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Cited By

Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Mastoras AManis G(2015)Ariadne - Directive-based parallelism extraction from recursive functionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2015.07.00986:C(16-28)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.jpdc.2015.07.009
Grelck C(2015)Single Assignment C (SAC)Central European Functional Programming School10.1007/978-3-030-28346-9_7(207-282)Online publication date: 6-Jul-2015
https://dl.acm.org/doi/10.1007/978-3-030-28346-9_7
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Index Terms

Implementation and evaluation of a microthread architecture
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
      2. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. General and reference
  1. Cross-computing tools and techniques
    1. Design

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cover image Journal of Systems Architecture: the EUROMICRO Journal

Journal of Systems Architecture: the EUROMICRO Journal Volume 55, Issue 3

March, 2009

63 pages

ISSN:1383-7621

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Copyright © Elsevier B.V. © 2008.

Publisher

Elsevier North-Holland, Inc.

United States

Publication History

Published: 01 March 2009

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Cited By

Uddin I(2017)One-IPC high-level simulation of microthreaded many-core architecturesInternational Journal of High Performance Computing Applications10.1177/109434201558449531:2(152-162)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1177/1094342015584495
Mastoras AManis G(2015)Ariadne - Directive-based parallelism extraction from recursive functionsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2015.07.00986:C(16-28)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1016/j.jpdc.2015.07.009
Grelck C(2015)Single Assignment C (SAC)Central European Functional Programming School10.1007/978-3-030-28346-9_7(207-282)Online publication date: 6-Jul-2015
https://dl.acm.org/doi/10.1007/978-3-030-28346-9_7
Wallentowitz SWild THerkersdorf A(2013)HW-OSQMProceedings of the 26th international conference on Architecture of Computing Systems10.1007/978-3-642-36424-2_24(280-291)Online publication date: 19-Feb-2013
https://dl.acm.org/doi/10.1007/978-3-642-36424-2_24
van der Veldt Kvan Nieuwpoort RVarbanescu AJesshope CVarbanescu Avan Nieuwpoort RZwart SVarbanescu A(2012)A polyphase filter for GPUs and multi-core processorsProceedings of the 2012 workshop on High-Performance Computing for Astronomy Date10.1145/2286976.2286986(33-40)Online publication date: 18-Jun-2012
https://dl.acm.org/doi/10.1145/2286976.2286986
Poss RLankamp MUddin MSýkora JKafka LPérez DNiar SSilvano CAbhari M(2012)Heterogeneous integration to simplify many-core architecture simulationsProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162134(17-24)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162134
Uddin MJesshope Cvan Tol MPoss RPérez DNiar SSilvano CAbhari M(2012)Collecting signatures to model latency tolerance in high-level simulations of microthreaded coresProceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2162131.2162132(1-8)Online publication date: 23-Jan-2012
https://dl.acm.org/doi/10.1145/2162131.2162132
Grelck C(2011)Single assignment C (SAC) high productivity meets high performanceProceedings of the 4th Summer School conference on Central European Functional Programming School10.1007/978-3-642-32096-5_5(207-278)Online publication date: 14-Jun-2011
https://dl.acm.org/doi/10.1007/978-3-642-32096-5_5
Herhut SJoslin CScholz SPoss RGrelck C(2010)Concurrent non-deferred reference counting on the MicrogridProceedings of the 22nd international conference on Implementation and application of functional languages10.5555/2050135.2050147(185-202)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.5555/2050135.2050147
Bernard TGrelck CHicks MJesshope CPoss R(2010)Resource-agnostic programming for many-core microgridsProceedings of the 2010 conference on Parallel processing10.5555/2031978.2031994(109-116)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.5555/2031978.2031994
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