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VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

Published: 01 November 2022 Publication History

Abstract

Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.

Highlights

A reduced hardware complexity architecture of 5/3 and 9/7 lifting bi-orthogonal DWT
Uses Distribute Arithmetic and Canonical Signed Digit to give minimum realization
Functionality verified using Altera DE2-115 Cyclon IV FPGA
Hardware results compared with other optimized DWT architectures

References

[1]
Pouyanfar S., Yang Y., Chen S.-C., Shyu M.-L., Iyengar S., Multimedia big data analytics: A survey, ACM Comput. Surv. 51 (1) (2018) 1–34.
[2]
Wang Z., Mao S., Yang L., Tang P., A survey of multimedia big data, China Commun. 15 (1) (2018) 155–176.
[3]
Hossain M.S., Muhammad G., Abdul W., Song B., Gupta B., Cloud-assisted secure video transmission and sharing framework for smart cities, Future Gener. Comput. Syst. 83 (2018) 596–606.
[4]
Biemond J., Mersereau R.M., Image and video processing, Video, Speech, and Audio Signal Processing and Associated Standards (2018).
[5]
Schremmer C., Multimedia Applications of the Wavelet Transform, (Ph.D. thesis) 2002.
[6]
Aksehir Y., Erdayandi K., Ozcan T.Z., Hamzaoglu I., A low energy adaptive motion estimation hardware for H. 264 multiview video coding, J. Real-Time Image Process. 15 (1) (2018) 3–12.
[7]
Alam M., Badawy W., Dimitrov V., Jullien G., An efficient architecture for a lifted 2D biorthogonal DWT, J. VLSI Signal Process. Syst. Signal Image Video Technol. 40 (3) (2005) 335–342.
[8]
Pang C.-Y., Zhou R.-G., Hu B.-Q., Hu W., El-Rafei A., Signal and image compression using quantum discrete cosine transform, Inform. Sci. 473 (2019) 121–141.
[9]
Alam M., Badawy W., Jullien G., A new time distributed DCT architecture for MPEG-4 hardware reference model, IEEE Trans. Circuits Syst. Video Technol. 15 (5) (2005) 726–730.
[10]
Lama R.K., Shin S., Kang M., Kwon G.-R., Choi M.-R., Interpolation using wavelet transform and discrete cosine transform for high resolution display, in: 2016 IEEE International Conference on Consumer Electronics (ICCE), IEEE, 2016, pp. 184–186.
[11]
Alam M., Onen D., Badawy W., Jullien G., VLSI prototyping of low-complexity wavelet transform on FPGA, in: IEEE CCECE2002. Canadian Conference on Electrical and Computer Engineering. Conference Proceedings, Vol. 1, IEEE, 2002, pp. 412–415.
[12]
Gautam B., Image Compression Using Discrete Cosine Transform & Discrete Wavelet Transform, Department of Computer Science and Engineering, National Institute of Technology, Rourkela, 2010.
[13]
Alam M., Badawy W., Dimitrov V., Jullien G., Efficient direct 2D architecture for lifted biorthogonal DWT, in: 2003 IEEE Workshop on Signal Processing Systems, IEEE, 2003, pp. 340–345.
[14]
Lian C.-J., Chen K.-F., Chen H.-H., Chen L.-G., Lifting based discrete wavelet transform architecture for JPEG2000, in: ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems, Vol. 2, IEEE, 2001, pp. 445–448.
[15]
Alam M., Badawy W., Jullien G., Time distributed DCT architecture for multimedia applications, in: 2003 IEEE International Conference on Consumer Electronics, 2003. ICCE., IEEE, 2003, pp. 166–167.
[16]
Taubman D.S., Marcellin M.W., JPEG2000: Image compression fundamentals, Stand. Pract. 11 (2) (2002).
[17]
Alam M., DWT and DCT Parallel-Pipelined Architectures for Real Time Applications, Calgary, 2003.
[18]
Skodras A., Christopoulos C., Ebrahimi T., The JPEG 2000 still image compression standard, IEEE Signal Process. Mag. 18 (5) (2001) 36–58.
[19]
LeGall D.J., Sub-band coding of images with low computational complexity, 1989, US Patent 4,829,378.
[20]
Martina M., Masera G., Multiplierless, folded 9/7–5/3 wavelet VLSI architecture, IEEE Trans. Circuits Syst. II: Express Br. 54 (9) (2007) 770–774.
[21]
Aziz F., Javed S., Gardezi S.E.I., Younis C.J., Alam M., Design and implementation of efficient DA architecture for LeGall 5/3 DWT, in: 2018 International Symposium on Recent Advances in Electrical Engineering (RAEE), IEEE, 2018, pp. 1–5.
[22]
Gardezi S.E.I., Aziz F., Javed S., Younis C.J., Alam M., Massoud Y., Design and VLSI implementation of CSD based DA architecture for 5/3 DWT, in: 2019 16th International Bhurban Conference on Applied Sciences and Technology (IBCAST), IEEE, 2019, pp. 548–552.
[23]
Javed S., Younis C.J., Alam M., Massoud Y., VLSI architecture design of 9/7 discrete wavelet transform for image processing, in: 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE, 2019, pp. 686–689.
[24]
Edavoor P.J., Rahulkar A.D., Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank, IET Image Process. 13 (5) (2019) 785–793.
[25]
Huang C.-T., Tseng P.-C., Chen L.-G., Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform, IEEE Trans. Signal Process. 52 (4) (2004) 1080–1089.
[26]
Rioul O., Vetterli M., Wavelets and signal processing, IEEE Signal Process. Mag. 8 (4) (1991) 14–38.
[27]
Sweldens W., The lifting scheme: A custom-design construction of biorthogonal wavelets, Appl. Comput. Harmon. Anal. 3 (2) (1996) 186–200.
[28]
Jou J.M., Shiau Y.-H., Liu C.-C., Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme, in: ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems, Vol. 2, IEEE, 2001, pp. 529–532.
[29]
Avizienis A., Signed-digit numbe representations for fast parallel arithmetic, IRE Trans. Electron. Comput. (3) (1961) 389–400.
[30]
Hewlitt R.M., Swartzlantler E., Canonical signed digit representation for FIR digital filters, in: 2000 IEEE Workshop on Signal Processing Systems. SiPS 2000. Design and Implementation, IEEE, 2000, pp. 416–426.
[31]
Subasi A., Yaman E., Emg signal classification using discrete wavelet transform and rotation forest, in: International Conference on Medical and Biological Engineering, Springer, 2019, pp. 29–35.
[32]
Wu B.-F., Lin C.-F., A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec, IEEE Trans. Circuits Syst. Video Technol. 15 (12) (2005) 1615–1628.
[33]
Kotteri K.A., Bell A.E., Carletta J.E., Design of multiplierless, high-performance, wavelet filter banks with image compression applications, IEEE Trans. Circuits Syst. I. Regul. Pap. 51 (3) (2004) 483–494.
[34]
Sowmya K., Sonali S., Nagabhushanam M., Optimized DA based DWT-IDWT for image compression, Int. J. Concept. Electr. Electron. Eng. 1 (1) (2013) 67–71.
[35]
Alam M., Rahman C.A., Badawy W., Jullien G., Efficient distributed arithmetic based DWT architecture for multimedia applications, in: The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings., IEEE, 2003, pp. 333–336.

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      Published In

      cover image Integration, the VLSI Journal
      Integration, the VLSI Journal  Volume 87, Issue C
      Nov 2022
      378 pages

      Publisher

      Elsevier Science Publishers B. V.

      Netherlands

      Publication History

      Published: 01 November 2022

      Author Tags

      1. VLSI
      2. Lifting scheme
      3. Distributed arithmetic
      4. Canonical signed digit
      5. Discrete Wavelet Transform

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