article

A Framework for Run-time Reconfigurable Systems

Authors:

Michael Eisenring,

Marco PlatznerAuthors Info & Claims

The Journal of Supercomputing, Volume 21, Issue 2

Pages 145 - 159

https://doi.org/10.1023/A:1013627403946

Published: 25 February 2002 Publication History

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Abstract

We present a framework for run-time reconfigurable systems. The framework provides a methodology and a design representation which allow to plug in different design and implementation tools. Front-end tools cover design capture, temporal partitioning and scheduling; back-end tools provide reconfiguration control, communication channel generation, estimation, and the final code composition. This paper elaborates on two of the framework's main issues: First, we discuss the design representation comprising aspects of the problem, the target architecture, and the communication channels. Second, we present a hierarchical approach to reconfiguration control in multi-FPGA systems.

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Cited By

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Sababha BAlqudah Y(2018)A Reconfiguration-Based Fault-Tolerant Anti-Lock Brake-by-Wire SystemACM Transactions on Embedded Computing Systems10.1145/324217817:5(1-13)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3242178
Carvalho ECalazans NBrião EMoraes FNatividade da Silva Barros EWagner FCarro LRammig F(2004)PaDReHProceedings of the 17th symposium on Integrated circuits and system design10.1145/1016568.1016580(10-15)Online publication date: 4-Sep-2004
https://dl.acm.org/doi/10.1145/1016568.1016580
Heath LRibbens CPemmaraju S(2004)Processor-efficient sparse matrix-vector multiplicationComputers & Mathematics with Applications10.1016/j.camwa.2003.06.00948:3-4(589-608)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1016/j.camwa.2003.06.009
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Index Terms

A Framework for Run-time Reconfigurable Systems
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 21, Issue 2

February 2002

95 pages

ISSN:0920-8542

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Kluwer Academic Publishers

United States

Publication History

Published: 25 February 2002

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Sababha BAlqudah Y(2018)A Reconfiguration-Based Fault-Tolerant Anti-Lock Brake-by-Wire SystemACM Transactions on Embedded Computing Systems10.1145/324217817:5(1-13)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3242178
Carvalho ECalazans NBrião EMoraes FNatividade da Silva Barros EWagner FCarro LRammig F(2004)PaDReHProceedings of the 17th symposium on Integrated circuits and system design10.1145/1016568.1016580(10-15)Online publication date: 4-Sep-2004
https://dl.acm.org/doi/10.1145/1016568.1016580
Heath LRibbens CPemmaraju S(2004)Processor-efficient sparse matrix-vector multiplicationComputers & Mathematics with Applications10.1016/j.camwa.2003.06.00948:3-4(589-608)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1016/j.camwa.2003.06.009
Edwards MGreen P(2003)Run-time support for dynamically reconfigurable computing systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(03)00068-749:4-6(267-281)Online publication date: 1-Sep-2003
https://dl.acm.org/doi/10.1016/S1383-7621%2803%2900068-7

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Recommendations

Modeling and optimizing run-time reconfiguration using evolutionary computation

Designing Run-Time Reconfigurable Systems with JHDL

Issues in wireless video coding using run-time-reconfigurable FPGAs

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