article

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis

Authors:

Naren Narasimhan,

Rajesh Radhakrishnan,

Sriram Govindarajan,

Ranga VemuriAuthors Info & Claims

Formal Methods in System Design, Volume 19, Issue 3

Pages 237 - 273

https://doi.org/10.1023/A:1011250531814

Published: 01 October 2001 Publication History

Abstract

This paper presents a formal specification and a proof of correctness for the widely-used Force-Directed List Scheduling (FDLS) algorithm for resource-constrained scheduling of data flow graphs in high-level synthesis systems. The proof effort is conducted using a higher-order logic theorem prover. During the proof effort many interesting properties of the FDLS algorithm are discovered. These properties are formally stated and proved in a higher-order logic theorem proving environment. These properties constitute a detailed set of formal assertions and invariants that should hold at various steps in the FDLS algorithm. They are then inserted as programming assertions in the implementation of the FDLS algorithm in a production-strength high-level synthesis system. When turned on, the programming assertions (1) certify whether a specific run of the FDLS algorithm produced correct schedules and, (2) in the event of failure, help discover and isolate programming errors in the FDLS implementation.

We present a detailed example and several experiments to demonstrate the effectiveness of these assertions in discovering and isolating errors. Based on this experience, we discuss the role of the formal theorem proving exercise in developing a useful set of assertions for embedding in the scheduler code and argue that in the absence of such a formal proof checking effort, discovering such a useful set of assertions would have been an arduous if not impossible task.

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Cited By

Kundu SLerner SGupta R(2019)Translation validation of high-level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204288929:4(566-579)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2010.2042889
Yang ZHao KCong KLei LRay SXie FFanucci LTeich J(2016)Validating scheduling transformation for behavioral synthesisProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972192(1652-1657)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972192
Li TGuo YLiu WTang MAyala JJones AMadden PCoskun A(2013)Translation validation of scheduling in high level synthesisProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483070(101-106)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483070
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Index Terms

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis
1. Hardware
  1. Hardware test
  2. Robustness
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Scheduling algorithms
    2. Online algorithms
      1. Online learning algorithms
        Scheduling algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning
        Sequential decision making

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cover image Formal Methods in System Design

Formal Methods in System Design Volume 19, Issue 3

November 2001

90 pages

ISSN:0925-9856

Issue’s Table of Contents

Copyright © Copyright © 2001 Kluwer Academic Publishers.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 October 2001

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Cited By

Kundu SLerner SGupta R(2019)Translation validation of high-level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204288929:4(566-579)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2010.2042889
Yang ZHao KCong KLei LRay SXie FFanucci LTeich J(2016)Validating scheduling transformation for behavioral synthesisProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972192(1652-1657)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972192
Li TGuo YLiu WTang MAyala JJones AMadden PCoskun A(2013)Translation validation of scheduling in high level synthesisProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483070(101-106)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483070
Lee CShih CHuang JJou J(2011)Equivalence checking of scheduling with speculative code transformations in high-level synthesisProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950917(497-502)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950917
Kundu SLerner SGupta R(2008)Validating High-Level SynthesisProceedings of the 20th international conference on Computer Aided Verification10.1007/978-3-540-70545-1_44(459-472)Online publication date: 7-Jul-2008
https://dl.acm.org/doi/10.1007/978-3-540-70545-1_44
Handa MRadhakrishnan RMukherjee MVemuri R(2003)A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA DesignsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835601Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835601

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